Re: [U-Boot] [PATCH 3/3] spi: cadence_qspi_apb: Make flash writes 32 bit aligned

On Tuesday 09 January 2018 11:31 AM, Goldschmidt Simon wrote: > On Mon, 08/01/2018 12:18, Vignesh R wrote: >> Make flash writes 32 bit aligned by using bounce buffers to deal with non 32 >> bit >> aligned buffers. Allocate a 512 byte bounce buffer (max known page size >> currently) for this

Re: [U-Boot] [PATCH 3/3] spi: cadence_qspi_apb: Make flash writes 32 bit aligned

On Mon, 08/01/2018 12:18, Vignesh R wrote: > Make flash writes 32 bit aligned by using bounce buffers to deal with non 32 > bit > aligned buffers. Allocate a 512 byte bounce buffer (max known page size > currently) for this case. Looking at drivers/mtd/spi/sf_dataflash.c, I see at least one chip

[U-Boot] [PATCH 3/3] spi: cadence_qspi_apb: Make flash writes 32 bit aligned

Make flash writes 32 bit aligned by using bounce buffers to deal with non 32 bit aligned buffers. Allocate a 512 byte bounce buffer (max known page size currently) for this case. This is required because as per TI K2G TRM[1], the external master is only permitted to issue 32-bit data interface