Re: [U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

2015-05-18 Thread Bin Meng
Hi Simon, On Tue, May 5, 2015 at 10:05 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 4 May 2015 at 00:27, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Tue, Apr 28, 2015 at 10:05 PM, Simon Glass s...@chromium.org wrote: Hi Bin, On 27 April 2015 at 00:16, Bin Meng

Re: [U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

2015-05-04 Thread Bin Meng
Hi Simon, On Tue, Apr 28, 2015 at 10:05 PM, Simon Glass s...@chromium.org wrote: Hi Bin, On 27 April 2015 at 00:16, Bin Meng bmeng...@gmail.com wrote: Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are

Re: [U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

2015-05-04 Thread Simon Glass
Hi Bin, On 4 May 2015 at 00:27, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Tue, Apr 28, 2015 at 10:05 PM, Simon Glass s...@chromium.org wrote: Hi Bin, On 27 April 2015 at 00:16, Bin Meng bmeng...@gmail.com wrote: Intel Quark SoC has the same interrupt routing mechanism as the

Re: [U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

2015-04-28 Thread Simon Glass
Hi Bin, On 27 April 2015 at 00:16, Bin Meng bmeng...@gmail.com wrote: Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng bmeng...@gmail.com

[U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

2015-04-27 Thread Bin Meng
Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng bmeng...@gmail.com --- arch/x86/cpu/quark/Makefile | 2 +-