On 03/23/2012 09:24 PM, Prabhakar Kushwaha wrote:
On Friday 23 March 2012 11:44 PM, Scott Wood wrote:
On 03/23/2012 06:44 AM, Prabhakar Kushwaha wrote:
After internal discussion we can have following settings
for non-RAMBOOT(NOR boot) == I + G
for RAMBOOT == I, cache inhibited is required
Hi Scott,
On Friday 23 March 2012 01:13 AM, Scott Wood wrote:
On 03/22/2012 12:52 AM, Prabhakar Kushwaha wrote:
Hi Scott,
Please find my reply in-lined
On Thursday 22 March 2012 01:22 AM, Scott Wood wrote:
On 03/20/2012 11:43 PM, Prabhakar Kushwaha wrote:
Debugging of e500 and e500v1
On 03/23/2012 06:44 AM, Prabhakar Kushwaha wrote:
Hi Scott,
On Friday 23 March 2012 01:13 AM, Scott Wood wrote:
On 03/22/2012 12:52 AM, Prabhakar Kushwaha wrote:
Hi Scott,
Please find my reply in-lined
On Thursday 22 March 2012 01:22 AM, Scott Wood wrote:
On 03/20/2012 11:43 PM,
On Friday 23 March 2012 11:44 PM, Scott Wood wrote:
On 03/23/2012 06:44 AM, Prabhakar Kushwaha wrote:
Hi Scott,
On Friday 23 March 2012 01:13 AM, Scott Wood wrote:
On 03/22/2012 12:52 AM, Prabhakar Kushwaha wrote:
Hi Scott,
Please find my reply in-lined
On Thursday 22 March 2012 01:22
On 03/22/2012 12:52 AM, Prabhakar Kushwaha wrote:
Hi Scott,
Please find my reply in-lined
On Thursday 22 March 2012 01:22 AM, Scott Wood wrote:
On 03/20/2012 11:43 PM, Prabhakar Kushwaha wrote:
Debugging of e500 and e500v1 processer requires debug exception
vecter (IVPR +
IVOR15) to
On 03/22/2012 02:51 PM, Timur Tabi wrote:
Scott Wood wrote:
For your kind information : in start.S, label label
create_ccsr_new_tlb, create_ccsr_old_tlb uses MAS7 without
CONFIG_ENABLE_36BIT_PHYS #define.
It should be fixed ??
Yes, it should be fixed. That was a fairly recent change
Scott Wood wrote:
Either it's needed, or we should get rid of CONFIG_ENABLE_36BIT_PHYS
entirely. Either way, we should test the results on e500v1 hardware.
That macro conditionally enables support for MAS7:
#if defined(CONFIG_ENABLE_36BIT_PHYS)
ori r0,r0,HID0_ENMAS7@l /*
On 03/22/2012 02:56 PM, Timur Tabi wrote:
Scott Wood wrote:
Either it's needed, or we should get rid of CONFIG_ENABLE_36BIT_PHYS
entirely. Either way, we should test the results on e500v1 hardware.
That macro conditionally enables support for MAS7:
#if defined(CONFIG_ENABLE_36BIT_PHYS)
Scott Wood wrote:
For your kind information : in start.S, label label
create_ccsr_new_tlb, create_ccsr_old_tlb uses MAS7 without
CONFIG_ENABLE_36BIT_PHYS #define.
It should be fixed ??
Yes, it should be fixed. That was a fairly recent change and perhaps
e500v1 has not been tested
On 03/20/2012 11:43 PM, Prabhakar Kushwaha wrote:
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 091af7c..d0b15a4 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -1,5 +1,5 @@
Hi Scott,
On Wednesday 21 March 2012 10:04 PM, Scott Wood wrote:
On 03/20/2012 11:43 PM, Prabhakar Kushwaha wrote:
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 091af7c..d0b15a4 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
On 03/21/2012 12:04 PM, Prabhakar Kushwaha wrote:
Hi Scott,
On Wednesday 21 March 2012 10:04 PM, Scott Wood wrote:
I don't see anywhere in this patchset where you set
CONFIG_SYS_PPC_E500_DEBUG_TLB on any actual board.
This CONFIG_SYS_PPC_E500_DEBUG_TLB is defined in
On 03/20/2012 11:43 PM, Prabhakar Kushwaha wrote:
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.
While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e.
Hi Scott,
Please find my reply in-lined
On Thursday 22 March 2012 01:22 AM, Scott Wood wrote:
On 03/20/2012 11:43 PM, Prabhakar Kushwaha wrote:
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.
While executing in
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.
While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to
fetch an instruction
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