Argh, forgot to copy the list.
>>
>>
>> Enabling it on individual SoCs based on verification conflicts with
>> putting this in the core-specific config area.
>>
>> Just test with a reasonable sample of SoCs, grep for TLB assignments to
>> look for any conflicts, and then enable it in the generic e
Hi Scott,
On Wednesday 25 April 2012 08:20 PM, Scott Wood wrote:
On 04/24/2012 11:05 PM, Andy Fleming wrote:
On Tue, Apr 24, 2012 at 10:48 PM, Prabhakar Kushwaha
wrote:
Hi,
On Wednesday 25 April 2012 02:50 AM, Andy Fleming wrote:
On Tue, Apr 24, 2012 at 4:10 PM, Scott Wood
wrote:
On
On 04/24/2012 11:05 PM, Andy Fleming wrote:
On Tue, Apr 24, 2012 at 10:48 PM, Prabhakar Kushwaha
wrote:
Hi,
On Wednesday 25 April 2012 02:50 AM, Andy Fleming wrote:
On Tue, Apr 24, 2012 at 4:10 PM, Scott Wood
wrote:
On 04/24/2012 03:45 PM, Andy Fleming wrote:
On Mon, Mar 26, 2012 at
On Tue, Apr 24, 2012 at 10:48 PM, Prabhakar Kushwaha
wrote:
> Hi,
>
>
>
> On Wednesday 25 April 2012 02:50 AM, Andy Fleming wrote:
>>
>> On Tue, Apr 24, 2012 at 4:10 PM, Scott Wood
>> wrote:
>>>
>>> On 04/24/2012 03:45 PM, Andy Fleming wrote:
On Mon, Mar 26, 2012 at 4:00 AM, Prabhakar K
Hi,
On Wednesday 25 April 2012 02:50 AM, Andy Fleming wrote:
On Tue, Apr 24, 2012 at 4:10 PM, Scott Wood wrote:
On 04/24/2012 03:45 PM, Andy Fleming wrote:
On Mon, Mar 26, 2012 at 4:00 AM, Prabhakar Kushwaha
@@ -107,6 +107,7 @@
#define CONFIG_MAX_CPUS1
#define CO
On Tue, Apr 24, 2012 at 4:10 PM, Scott Wood wrote:
> On 04/24/2012 03:45 PM, Andy Fleming wrote:
>> On Mon, Mar 26, 2012 at 4:00 AM, Prabhakar Kushwaha
>>> @@ -107,6 +107,7 @@
>>> #define CONFIG_MAX_CPUS 1
>>> #define CONFIG_FSL_SDHC_V2_3
>>> #define CONFIG_SYS_FSL_NUM_LA
On 04/24/2012 03:45 PM, Andy Fleming wrote:
> On Mon, Mar 26, 2012 at 4:00 AM, Prabhakar Kushwaha
>> @@ -107,6 +107,7 @@
>> #define CONFIG_MAX_CPUS1
>> #define CONFIG_FSL_SDHC_V2_3
>> #define CONFIG_SYS_FSL_NUM_LAWS12
>> +#define CONFIG_SYS_PPC_E500_DEBUG_
On Mon, Mar 26, 2012 at 4:00 AM, Prabhakar Kushwaha
wrote:
> Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
> IVOR15) to have valid and fetchable OP code.
>
> While executing in translated space (AS=1), whenever a debug exception is
> generated, the MSR[DS/IS] gets
Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.
While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to
fetch an instruction fro
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