Yes, it's an erratum. But I don't have the erratum number from the document. I
will connect the hardware team to check whether there is an erratum number.
Thanks.
Best Regards,
Yuan Yao
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, November 05,
On 10/21/2015 03:14 AM, Yuan Yao wrote:
> EDDRTQCFG Registers are Integration Strap values which controls
> performance parameters for DDR Controller.
>
> The bit 25 is used to disable priorities within DDR since DDR
> are connected backwards on Rev2.0.
>
> Signed-off-by: Yuan Yao
> ---
> arc
EDDRTQCFG Registers are Integration Strap values which controls
performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR
are connected backwards on Rev2.0.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 13 -
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