DESCRIPTION:
If the DF bit is set prior to a hardware reset, the PLL will continue to
divide CLKIN by 2 after the hardware reset, but the DF bit itself will be
cleared in the PLL_CTL register.
WORKAROUND:
Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by
2 after reset.
Signed-off-by: Mike Frysinger <vap...@gentoo.org>
---
cpu/blackfin/initcode.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index d44c6a6..7f54860 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -401,7 +401,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)
/* Only reprogram when needed to avoid triggering unnecessary
* PLL relock sequences.
*/
- if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
+ if (ANOMALY_05000242 || bfin_read_PLL_CTL() !=
CONFIG_PLL_CTL_VAL) {
serial_putc('!');
bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
asm("idle;");
--
1.6.2.2
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