Re: [U-Boot] [PATCH 5/8] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

Hi Rick, On Thu, Oct 31, 2019 at 10:31 AM Rick Chen wrote: > > Hi Bin > > > > > Hi Rick, > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote: > > > > > > From: Rick Chen > > > > > > The mcache_ctl csr only can be manipulated in M mode. > > > Add SPL_RISCV_MMODE for U-Boot SPL to control cache >

Re: [U-Boot] [PATCH 5/8] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

Hi Bin > > Hi Rick, > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote: > > > > From: Rick Chen > > > > The mcache_ctl csr only can be manipulated in M mode. > > Add SPL_RISCV_MMODE for U-Boot SPL to control cache > > operation. > > > > Signed-off-by: Rick Chen > > Cc: KC Lin > > Cc: Alan Kao >

Re: [U-Boot] [PATCH 5/8] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

Hi Rick, On Fri, Oct 25, 2019 at 2:18 PM Andes wrote: > > From: Rick Chen > > The mcache_ctl csr only can be manipulated in M mode. > Add SPL_RISCV_MMODE for U-Boot SPL to control cache > operation. > > Signed-off-by: Rick Chen > Cc: KC Lin > Cc: Alan Kao > --- > arch/riscv/cpu/ax25/cache.c

[U-Boot] [PATCH 5/8] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

From: Rick Chen The mcache_ctl csr only can be manipulated in M mode. Add SPL_RISCV_MMODE for U-Boot SPL to control cache operation. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/cpu/ax25/cache.c | 60 ++--- 1 file changed, 46 inserti