Re: [U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2017-01-04 Thread Marek Vasut
On 01/04/2017 05:54 PM, Jagan Teki wrote: > On Wed, Jan 4, 2017 at 5:43 PM, Marek Vasut wrote: >> On 01/04/2017 05:40 PM, Jagan Teki wrote: >>> On Wed, Jan 4, 2017 at 5:22 PM, Marek Vasut wrote: On 01/04/2017 04:53 PM, Jagan Teki wrote: > On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R wrote:

Re: [U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2017-01-04 Thread Jagan Teki
On Wed, Jan 4, 2017 at 5:43 PM, Marek Vasut wrote: > On 01/04/2017 05:40 PM, Jagan Teki wrote: >> On Wed, Jan 4, 2017 at 5:22 PM, Marek Vasut wrote: >>> On 01/04/2017 04:53 PM, Jagan Teki wrote: On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R wrote: > > > On Tuesday 03 January 2017 07

Re: [U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2017-01-04 Thread Marek Vasut
On 01/04/2017 05:40 PM, Jagan Teki wrote: > On Wed, Jan 4, 2017 at 5:22 PM, Marek Vasut wrote: >> On 01/04/2017 04:53 PM, Jagan Teki wrote: >>> On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R wrote: On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote: > On Tue, Jan 3, 2017 at 2:35

Re: [U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2017-01-04 Thread Jagan Teki
On Wed, Jan 4, 2017 at 5:22 PM, Marek Vasut wrote: > On 01/04/2017 04:53 PM, Jagan Teki wrote: >> On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R wrote: >>> >>> >>> On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote: On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh wrote: > > > On 12/21/

Re: [U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2017-01-04 Thread Marek Vasut
On 01/04/2017 04:53 PM, Jagan Teki wrote: > On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R wrote: >> >> >> On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote: >>> On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh wrote: On 12/21/2016 10:42 AM, Vignesh R wrote: > According to Section 11.

Re: [U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2017-01-04 Thread Jagan Teki
On Wed, Jan 4, 2017 at 5:02 AM, Vignesh R wrote: > > > On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote: >> On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh wrote: >>> >>> >>> On 12/21/2016 10:42 AM, Vignesh R wrote: According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC T

Re: [U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2017-01-03 Thread Vignesh R
On Tuesday 03 January 2017 07:40 PM, Jagan Teki wrote: > On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh wrote: >> >> >> On 12/21/2016 10:42 AM, Vignesh R wrote: >>> According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC >>> TRM SPRUHY8D[1], the external master is only permitted to iss

Re: [U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2017-01-03 Thread Jagan Teki
On Tue, Jan 3, 2017 at 2:35 PM, R, Vignesh wrote: > > > On 12/21/2016 10:42 AM, Vignesh R wrote: >> According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC >> TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit >> data interface writes until the last word of an ind

Re: [U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2017-01-03 Thread R, Vignesh
On 12/21/2016 10:42 AM, Vignesh R wrote: > According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC > TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit > data interface writes until the last word of an indirect transfer > otherwise indirect writes is known to fai

[U-Boot] [PATCH RESEND v2 1/2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

2016-12-20 Thread Vignesh R
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writ