Hi Philipp, >> +#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) >> +#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) >> +#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) >> +#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) >> +#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) >> + >> +#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) >> +#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000) > >This should use structure for I/O access. >Please refer to https://www.denx.de/wiki/U-Boot/CodingStyle for details.
I understand. It is a bit hard for me to convert them to structure based. I'll ask to see if our SoC team could generate that piece structure. Anyway if this last patch could not be accepted, I hope the rest patches could be in first. Regards, Peng. > >Regards, >Philipp. > -- _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
