Add i.MX7 PSCI system power off support, linux
kernel can use "poweroff" command to power off
system via SNVS, PMIC power will be disabled.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since v1:
use "bl" instead of "b" as we need the call to return back.
arch/arm/mach-imx/mx7/psci-mx7.c | 18 ++++++++++++++++++
arch/arm/mach-imx/mx7/psci.S | 7 +++++++
2 files changed, 25 insertions(+)
diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c
index 66f6db6..0e515f0 100644
--- a/arch/arm/mach-imx/mx7/psci-mx7.c
+++ b/arch/arm/mach-imx/mx7/psci-mx7.c
@@ -26,6 +26,12 @@
#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
+#define SNVS_LPCR 0x38
+#define BP_SNVS_LPCR_DP_EN 0x20
+#define BP_SNVS_LPCR_TOP 0x40
+
+#define CCM_CCGR_SNVS 0x4250
+
static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
{
writel(enable, GPC_IPS_BASE_ADDR + offset);
@@ -79,3 +85,15 @@ __secure void imx_system_reset(void)
{
writew(1 << 2, WDOG1_BASE_ADDR);
}
+
+__secure void imx_system_off(void)
+{
+ u32 val;
+
+ /* make sure SNVS clock is enabled */
+ writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
+
+ val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
+ val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
+ writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
+}
diff --git a/arch/arm/mach-imx/mx7/psci.S b/arch/arm/mach-imx/mx7/psci.S
index e23db24..bc2cd8a 100644
--- a/arch/arm/mach-imx/mx7/psci.S
+++ b/arch/arm/mach-imx/mx7/psci.S
@@ -50,4 +50,11 @@ psci_system_reset:
2: wfi
b 2b
+.globl psci_system_off
+psci_system_off:
+ bl imx_system_off
+
+3: wfi
+ b 3b
+
.popsection
--
1.9.1
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