From: Armando Visconti <armando.visco...@st.com>
This patch solves a TX/RX problem which happens at 10Mbps, due to the
fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between
two consecutive writes on the same register.
Signed-off-by: Armando Visconti <armando.visco...@st.com>
Signed-off-by: Amit Virdi <amit.vi...@st.com>
---
drivers/net/designware.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index fc14b70..933032c 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -175,8 +175,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
- writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf);
- writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf);
+ writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
return 0;
}
--
1.7.2.2
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