On 02/25/2015 02:55 PM, Nishanth Menon wrote:
Add workaround for Cortex-A15 ARM erratum 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second
Add workaround for Cortex-A15 ARM erratum 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a
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