Re: [U-Boot] [PATCH rev2] ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon

Dear John Rigby, In message <[EMAIL PROTECTED]> you wrote: > MPC5121 rev 2 silicon has a new register for controlling how long > CS is asserted after deassertion of ALE in multiplexed mode. > > The default is to assert CS together with ALE. The alternative > is to assert CS (ALEN+1)*LPC_CLK cloc

[U-Boot] [PATCH rev2] ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon

MPC5121 rev 2 silicon has a new register for controlling how long CS is asserted after deassertion of ALE in multiplexed mode. The default is to assert CS together with ALE. The alternative is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE. The default is wrong for the NOR flash a