The reset procedure works on watchdog timer while before it was modifying
TIMER_1 registers.
Tested on DM365.

Signed-off-by: Davide Bonfanti <davide.bonfa...@bticino.it>
---
 arch/arm/cpu/arm926ejs/davinci/reset.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.c 
b/arch/arm/cpu/arm926ejs/davinci/reset.c
index 968fb03..80f1ce9 100644
--- a/arch/arm/cpu/arm926ejs/davinci/reset.c
+++ b/arch/arm/cpu/arm926ejs/davinci/reset.c
@@ -16,7 +16,7 @@
 void reset_cpu(unsigned long a)
 {
  struct davinci_timer *const wdttimer =
-  (struct davinci_timer *)DAVINCI_TIMER1_BASE;
+  (struct davinci_timer *)DAVINCI_WDOG_BASE;
  writel(0x08, &wdttimer->tgcr);
  writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
  writel(0, &wdttimer->tim12);
-- 
1.7.9.5



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