Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS
and access is going via SCU device, enumerated via PCI.
For now, we add just a minimum support of PMIC device to allow enabling,
e.g. USB OTG, in the OS.
Signed-off-by: Andy Shevchenko
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.../asm/arch-tangier/acpi/southcluste
On Tue, Feb 5, 2019 at 7:07 PM Andy Shevchenko
wrote:
>
> Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS
> and access is going via SCU device, enumerated via PCI.
>
> For now, we add just a minimum support of PMIC device to allow enabling,
> e.g. USB OTG, in the OS.
>
> Signe
On Tue, Feb 12, 2019 at 2:18 PM Bin Meng wrote:
>
> On Tue, Feb 5, 2019 at 7:07 PM Andy Shevchenko
> wrote:
> >
> > Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS
> > and access is going via SCU device, enumerated via PCI.
> >
> > For now, we add just a minimum support of PM
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