On 11/05/2015 02:03 AM, York Sun wrote:
> This patch set revises the DDR driver to support higher speed for DDR4
> under heavy load (two dual-rank DIMMs) for four-chipselect interleaving.
> Single quad-rank DIMM is not supported yet.
>
>
> York Sun (7):
> driver/ddr/fsl: Update DDR4 RTT
On 11/11/2015 11:35 PM, Joakim Tjernlund wrote:
> On Thu, 2015-11-05 at 12:47 -0800, York Sun wrote:
>>
>> On 11/05/2015 11:53 AM, Joakim Tjernlund wrote:
>>> On Thu, 2015-11-05 at 10:29 -0800, York Sun wrote:
On 11/05/2015 10:19 AM, Joakim Tjernlund wrote:
> On Thu, 2015-11-05 at
On Thu, 2015-11-05 at 12:47 -0800, York Sun wrote:
>
> On 11/05/2015 11:53 AM, Joakim Tjernlund wrote:
> > On Thu, 2015-11-05 at 10:29 -0800, York Sun wrote:
> > >
> > > On 11/05/2015 10:19 AM, Joakim Tjernlund wrote:
> > > > On Thu, 2015-11-05 at 09:42 -0800, York Sun wrote:
> > > > >
> > > >
On Fri, 2015-11-06 at 02:24 +, Yuantian Tang wrote:
>
> > -Original Message-
> > From: York Sun [mailto:york...@freescale.com]
> > Sent: Friday, November 06, 2015 1:42 AM
> > To: Joakim Tjernlund ; Tang Yuantian-
> > B29983 ;
On Wed, 2015-11-04 at 10:03 -0800, York Sun wrote:
> This patch set revises the DDR driver to support higher speed for DDR4
> under heavy load (two dual-rank DIMMs) for four-chipselect interleaving.
> Single quad-rank DIMM is not supported yet.
Hi York
Seeing these patches reminds me about
On Thu, 2015-11-05 at 08:23 +, Yuantian Tang wrote:
> Hi Jocke,
>
> we achieved deep sleep mode that did exactly what you asked for.
> If waken up from deep sleep, soc will resume from uboot and re-initialized
> DDR controller with contents
> untouched.
> Please refer to
Hi Jocke,
we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR
controller with contents untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related
code.
Regards,
Yuantian
>
On 11/05/2015 01:55 AM, Joakim Tjernlund wrote:
> On Thu, 2015-11-05 at 08:23 +, Yuantian Tang wrote:
>> Hi Jocke,
>>
>> we achieved deep sleep mode that did exactly what you asked for.
>> If waken up from deep sleep, soc will resume from uboot and re-initialized
>> DDR controller with
On Thu, 2015-11-05 at 10:29 -0800, York Sun wrote:
>
> On 11/05/2015 10:19 AM, Joakim Tjernlund wrote:
> > On Thu, 2015-11-05 at 09:42 -0800, York Sun wrote:
> > >
> > > On 11/05/2015 01:55 AM, Joakim Tjernlund wrote:
> > > > On Thu, 2015-11-05 at 08:23 +, Yuantian Tang wrote:
> > > > > Hi
On Thu, 2015-11-05 at 09:42 -0800, York Sun wrote:
>
> On 11/05/2015 01:55 AM, Joakim Tjernlund wrote:
> > On Thu, 2015-11-05 at 08:23 +, Yuantian Tang wrote:
> > > Hi Jocke,
> > >
> > > we achieved deep sleep mode that did exactly what you asked for.
> > > If waken up from deep sleep, soc
On 11/05/2015 10:19 AM, Joakim Tjernlund wrote:
> On Thu, 2015-11-05 at 09:42 -0800, York Sun wrote:
>>
>> On 11/05/2015 01:55 AM, Joakim Tjernlund wrote:
>>> On Thu, 2015-11-05 at 08:23 +, Yuantian Tang wrote:
Hi Jocke,
we achieved deep sleep mode that did exactly what you
On 11/05/2015 11:53 AM, Joakim Tjernlund wrote:
> On Thu, 2015-11-05 at 10:29 -0800, York Sun wrote:
>>
>> On 11/05/2015 10:19 AM, Joakim Tjernlund wrote:
>>> On Thu, 2015-11-05 at 09:42 -0800, York Sun wrote:
On 11/05/2015 01:55 AM, Joakim Tjernlund wrote:
> On Thu, 2015-11-05 at
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Friday, November 06, 2015 1:42 AM
> To: Joakim Tjernlund ; Tang Yuantian-
> B29983 ; u-boot@lists.denx.de
> Cc: Kushwaha Prabhakar-B32579
This patch set revises the DDR driver to support higher speed for DDR4
under heavy load (two dual-rank DIMMs) for four-chipselect interleaving.
Single quad-rank DIMM is not supported yet.
York Sun (7):
driver/ddr/fsl: Update DDR4 RTT values
driver/ddr/fsl: Update DDR4 MR6 for Vref range
14 matches
Mail list logo