Re: [U-Boot] [PATCH v2] ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz

2008-09-21 Thread Wolfgang Denk
Dear Victor, in message <[EMAIL PROTECTED]> you wrote: > ... > + * Use these scan options for PLB bus greater than or equal 200MHz > + * else use the defaults. These options are known to return a cycle > + * delay of T2 or better with a 200MHz PLB bus. Scanning the > + * full list of WDTR/CLKTR s

[U-Boot] [PATCH v2] ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz

2008-09-16 Thread Victor Gallardo
Signed-off-by: Victor Gallardo <[EMAIL PROTECTED]> Signed-off-by: Adam Graham <[EMAIL PROTECTED]> --- v2: - Add comments on why this is need for 200MHz PLB bus - Minor coding style cleanup board/amcc/kilauea/kilauea.c| 31 +++ cpu/ppc4xx/4xx_ibm_ddr2_aut