On 02/14/2014 09:47 PM, Jim Lin wrote:
>
>
> 寄件者: Stefan Agner [ste...@agner.ch]
> 寄件日期: 2014年2月15日 上午 06:52
> 收件者: u-boot@lists.denx.de; Jim Lin; Tom Warren; swar...@wwwdotorg.org;
> s...@chromium.org; d...@lynxeye.de
> 主旨: Re: [PATCH v2] usb: tegra: Fix
寄件者: Stefan Agner [ste...@agner.ch]
寄件日期: 2014年2月15日 上午 06:52
收件者: u-boot@lists.denx.de; Jim Lin; Tom Warren; swar...@wwwdotorg.org;
s...@chromium.org; d...@lynxeye.de
主旨: Re: [PATCH v2] usb: tegra: Fix PHY configuration for Tegra 3
Am 2014-02-14 23:45, s
Am 2014-02-14 23:45, schrieb Stefan Agner:
> /* Select ULPI parallel interface */
> - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
> + if (!controller->has_hostpc) {
> + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
> +
On Tegra 3, the PTS (parallel transceiver select) and STS (serial
transceiver select) are part of the HOSTPC1_DEVLC_0 register rather
than PORTSC1_0 register. Since the reset configuration usually
matches the configured registers, this error did not show up on
Tegra 3 devices.
Also clear the force
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