The support for in-kernel (v4.20) "phy-reset-post-delay" property has
been implemented in u-boot's FEC IMX driver. It has the same range (1 to
1000ms) as in Linux.
Some PHYs require waiting some time after the reset to be accessible
via MII bus. This problem has been observed on mccmon6 board with KSZ9031
PHY IC, when DM_ETH was enabled (as DM slightly changes time between
PHY initialization and first access).
Signed-off-by: Lukasz Majewski <lu...@denx.de>
---
Changes in v2: None
drivers/net/fec_mxc.c | 11 +++++++++++
drivers/net/fec_mxc.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 1a59026a62..6305aa5c05 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1315,6 +1315,8 @@ static void fec_gpio_reset(struct fec_priv *priv)
dm_gpio_set_value(&priv->phy_reset_gpio, 1);
mdelay(priv->reset_delay);
dm_gpio_set_value(&priv->phy_reset_gpio, 0);
+ if (priv->post_reset_delay)
+ mdelay(priv->post_reset_delay);
}
}
#endif
@@ -1474,6 +1476,15 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev)
/* property value wrong, use default value */
priv->reset_delay = 1;
}
+
+ priv->post_reset_delay = dev_read_u32_default(dev,
+ "phy-reset-post-delay",
+ 0);
+ if (priv->post_reset_delay > 1000) {
+ printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
+ /* property value wrong, use default value */
+ priv->post_reset_delay = 0;
+ }
#endif
return 0;
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index e9a661f0a1..d069af533a 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -258,6 +258,7 @@ struct fec_priv {
#ifdef CONFIG_DM_GPIO
struct gpio_desc phy_reset_gpio;
uint32_t reset_delay;
+ u32 post_reset_delay;
#endif
#ifdef CONFIG_DM_ETH
u32 interface;
--
2.11.0
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