Re: [U-Boot] [PATCH v2 09/16] sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)

On Sun, 2014-08-03 at 05:32 +0300, Siarhei Siamashka wrote: The sun5i hardware (Allwinner A13) introduced configurable MBUS clock speed. Allwinner A13 uses only 16-bit data bus width to connect the external DRAM, which is halved compared to the 32-bit data bus of sun4i (Allwinner A10), so it

[U-Boot] [PATCH v2 09/16] sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)

The sun5i hardware (Allwinner A13) introduced configurable MBUS clock speed. Allwinner A13 uses only 16-bit data bus width to connect the external DRAM, which is halved compared to the 32-bit data bus of sun4i (Allwinner A10), so it does not make much sense to clock a wider internal bus at a very