On 16 October 2015 at 19:20, Otavio Salvador
wrote:
> On Fri, Oct 16, 2015 at 10:40 AM, Fabio Estevam wrote:
>> On Tue, Sep 29, 2015 at 10:54 AM, Jagan Teki wrote:
>>
Based on the implementation from Brian Norris
for the Linux kernel:
https://patchwork.ozlabs.org/patch/513041/
>>
On Fri, Oct 16, 2015 at 10:40 AM, Fabio Estevam wrote:
> On Tue, Sep 29, 2015 at 10:54 AM, Jagan Teki wrote:
>
>>> Based on the implementation from Brian Norris
>>> for the Linux kernel:
>>> https://patchwork.ozlabs.org/patch/513041/
>>
>> This patch is still under review, will see how it moves.
Hi Jagan,
On Tue, Sep 29, 2015 at 10:54 AM, Jagan Teki wrote:
>> Based on the implementation from Brian Norris
>> for the Linux kernel:
>> https://patchwork.ozlabs.org/patch/513041/
>
> This patch is still under review, will see how it moves.
Brian's patch is in linux-next now:
https://git.ker
On Tue, Sep 29, 2015 at 6:12 PM, Jagan Teki wrote:
>> +#ifdef CONFIG_SPI_FLASH_STM_PROTECT
>
> Drop this vendor specific macro on command code (usually command code
> deals generic-ness)
Ok
>
>> +static int do_spi_protect(int argc, char * const argv[])
>> +{
>> + int start, len, ret = 0;
On 29 September 2015 at 17:37, Fabio Estevam
wrote:
> Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
> status register that can protect selected regions of the SPI NOR.
>
> Take these bits into account when performing erase operations,
> making sure that the protected areas are sk
Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
status register that can protect selected regions of the SPI NOR.
Take these bits into account when performing erase operations,
making sure that the protected areas are skipped.
Introduce the CONFIG_SPI_FLASH_STM_PROTECT option that
On Tue, Sep 29, 2015 at 10:54 AM, Jagan Teki wrote:
> What if sf erase 0x3f 0x2 - it should skip first 0x1 from
> 0x3f and then erase next 0x1 from (0x3f+0x1) did you
> verify this?
On my case (M25P32) the 0x3f is the last sector (sector size is
0x1), so we ca
On 29 September 2015 at 17:37, Fabio Estevam
wrote:
> Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
> status register that can protect selected regions of the SPI NOR.
>
> Take these bits into account when performing erase operations,
> making sure that the protected areas are sk
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