On 09/07/2018 08:02 PM, Westergreen, Dalon wrote:
> On Fri, 2018-09-07 at 19:36 +0200, Marek Vasut wrote:
>> On 09/07/2018 06:40 PM, Dalon L Westergreen wrote:
>> On Fri, 2018-09-07 at 18:25 +0200, Marek Vasut wrote:
>> On 09/07/2018 06:15 PM, Dalon L Westergreen wrote:
>> On Thu, 2018-09-06 at
On Fri, 2018-09-07 at 19:36 +0200, Marek Vasut wrote:
> On 09/07/2018 06:40 PM, Dalon L Westergreen wrote:
> On Fri, 2018-09-07 at 18:25 +0200, Marek Vasut wrote:
> On 09/07/2018 06:15 PM, Dalon L Westergreen wrote:
> On Thu, 2018-09-06 at 23:56 +0200, Marek Vasut wrote:
> On 09/06/2018 11:26 PM,
On 09/07/2018 06:40 PM, Dalon L Westergreen wrote:
> On Fri, 2018-09-07 at 18:25 +0200, Marek Vasut wrote:
>> On 09/07/2018 06:15 PM, Dalon L Westergreen wrote:
>> On Thu, 2018-09-06 at 23:56 +0200, Marek Vasut wrote:
>> On 09/06/2018 11:26 PM, Dalon L Westergreen wrote:
>> On Thu, 2018-09-06 at
On Fri, 2018-09-07 at 18:25 +0200, Marek Vasut wrote:
> On 09/07/2018 06:15 PM, Dalon L Westergreen wrote:
> On Thu, 2018-09-06 at 23:56 +0200, Marek Vasut wrote:
> On 09/06/2018 11:26 PM, Dalon L Westergreen wrote:
> On Thu, 2018-09-06 at 15:41 +0200, Marek Vasut wrote:
> On 09/06/2018 03:39 PM,
On 09/07/2018 06:15 PM, Dalon L Westergreen wrote:
> On Thu, 2018-09-06 at 23:56 +0200, Marek Vasut wrote:
>> On 09/06/2018 11:26 PM, Dalon L Westergreen wrote:
>> On Thu, 2018-09-06 at 15:41 +0200, Marek Vasut wrote:
>> On 09/06/2018 03:39 PM, Dalon L Westergreen wrote:
>> On Thu, 2018-09-06 at
On Thu, 2018-09-06 at 23:56 +0200, Marek Vasut wrote:
> On 09/06/2018 11:26 PM, Dalon L Westergreen wrote:On Thu, 2018-09-06 at 15:41
> +0200, Marek Vasut wrote:On 09/06/2018 03:39 PM, Dalon L Westergreen wrote:On
> Thu, 2018-09-06 at 12:09 +0200, Marek Vasut wrote:On 09/06/2018 05:02 AM,
> Dalon
On 09/06/2018 11:26 PM, Dalon L Westergreen wrote:
> On Thu, 2018-09-06 at 15:41 +0200, Marek Vasut wrote:
>> On 09/06/2018 03:39 PM, Dalon L Westergreen wrote:
>> On Thu, 2018-09-06 at 12:09 +0200, Marek Vasut wrote:
>> On 09/06/2018 05:02 AM, Dalon Westergreen wrote:
>> Stratix10 requires a hex
On Thu, 2018-09-06 at 15:41 +0200, Marek Vasut wrote:
> On 09/06/2018 03:39 PM, Dalon L Westergreen wrote:
>
> On Thu, 2018-09-06 at 12:09 +0200, Marek Vasut wrote:
>
> On 09/06/2018 05:02 AM, Dalon Westergreen wrote:
> Stratix10 requires a hex image of the spl for boot. The hex
> image is
On 09/06/2018 07:40 PM, Dalon L Westergreen wrote:
> On Thu, 2018-09-06 at 15:41 +0200, Marek Vasut wrote:
>> On 09/06/2018 03:39 PM, Dalon L Westergreen wrote:
>> On Thu, 2018-09-06 at 12:09 +0200, Marek Vasut wrote:
>> On 09/06/2018 05:02 AM, Dalon Westergreen wrote:
>> Stratix10 requires a hex
On Thu, 2018-09-06 at 15:41 +0200, Marek Vasut wrote:
> On 09/06/2018 03:39 PM, Dalon L Westergreen wrote:
> On Thu, 2018-09-06 at 12:09 +0200, Marek Vasut wrote:
> On 09/06/2018 05:02 AM, Dalon Westergreen wrote:Stratix10 requires a hex image
> of the spl for boot. The heximage is added to the
On Thu, 2018-09-06 at 07:51 +0200, Simon Goldschmidt wrote:
> On Thu, Sep 6, 2018 at 5:04 AM Dalon Westergreen wrote:
>
> Stratix10 requires a hex image of the spl for boot. The heximage is added to
> the FPGA configuration image and loaded tothe processor memory by the
> configuration engine.
On 09/06/2018 03:39 PM, Dalon L Westergreen wrote:
> On Thu, 2018-09-06 at 12:09 +0200, Marek Vasut wrote:
>> On 09/06/2018 05:02 AM, Dalon Westergreen wrote:
>> Stratix10 requires a hex image of the spl for boot. The hex
>> image is added to the FPGA configuration image and loaded to
>> the
On Thu, 2018-09-06 at 12:09 +0200, Marek Vasut wrote:
> On 09/06/2018 05:02 AM, Dalon Westergreen wrote:
> Stratix10 requires a hex image of the spl for boot. The heximage is added to
> the FPGA configuration image and loaded tothe processor memory by the
> configuration engine.
> v2: -> add
On 09/06/2018 05:02 AM, Dalon Westergreen wrote:
> Stratix10 requires a hex image of the spl for boot. The hex
> image is added to the FPGA configuration image and loaded to
> the processor memory by the configuration engine.
>
> v2:
> -> add CONFIG_OF_EMBED to include dtb in elf
> ->
On Thu, Sep 6, 2018 at 5:04 AM Dalon Westergreen wrote:
>
> Stratix10 requires a hex image of the spl for boot. The hex
> image is added to the FPGA configuration image and loaded to
> the processor memory by the configuration engine.
Although not running a Stratix10, I also need a hex image
Stratix10 requires a hex image of the spl for boot. The hex
image is added to the FPGA configuration image and loaded to
the processor memory by the configuration engine.
v2:
-> add CONFIG_OF_EMBED to include dtb in elf
-> generate hex from elf source
Signed-off-by: Dalon Westergreen
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