On 18.07.2015 02:53, Scott Wood wrote:
> On Sat, 2015-07-18 at 02:38 +0300, Vladimir Zapolskiy wrote:
>> Hello Scott,
>>
>> On 18.07.2015 02:12, Scott Wood wrote:
>>> On Sat, 2015-07-18 at 01:47 +0300, Vladimir Zapolskiy wrote:
+/*
+ * LPC32xx has only one SLC NAND controller, don't utili
On Fri, 2015-07-17 at 18:53 -0500, Scott Wood wrote:
> On Sat, 2015-07-18 at 02:38 +0300, Vladimir Zapolskiy wrote:
> > Hello Scott,
> >
> > On 18.07.2015 02:12, Scott Wood wrote:
> > > On Sat, 2015-07-18 at 01:47 +0300, Vladimir Zapolskiy wrote:
> > > > +/*
> > > > + * LPC32xx has only one SLC NA
On Sat, 2015-07-18 at 02:38 +0300, Vladimir Zapolskiy wrote:
> Hello Scott,
>
> On 18.07.2015 02:12, Scott Wood wrote:
> > On Sat, 2015-07-18 at 01:47 +0300, Vladimir Zapolskiy wrote:
> > > +/*
> > > + * LPC32xx has only one SLC NAND controller, don't utilize
> > > + * CONFIG_SYS_NAND_SELF_INIT to
Hello Scott,
On 18.07.2015 02:12, Scott Wood wrote:
> On Sat, 2015-07-18 at 01:47 +0300, Vladimir Zapolskiy wrote:
>> +/* TAC register bits, be aware of overflows */
>> +#define TAC_W_RDY(n) (max_t(uint32_t, (n), 0xF) << 28)
>> +#define TAC_W_WIDTH(n) (max_t(uint32_t, (n), 0x
On Sat, 2015-07-18 at 01:47 +0300, Vladimir Zapolskiy wrote:
> +/* TAC register bits, be aware of overflows */
> +#define TAC_W_RDY(n) (max_t(uint32_t, (n), 0xF) << 28)
> +#define TAC_W_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 24)
> +#define TAC_W_HOLD(n)(max_t(u
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because acces
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