From: Laurentiu Tudor <laurentiu.tu...@nxp.com>

Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR
register in DCFG is not correctly forwarded to the SMMU.
The workaround consists in programming the eDMA ICID in the eDMA_AMQR
register in DCFG to 40.

Signed-off-by: Laurentiu Tudor <laurentiu.tu...@nxp.com>
---
Changes in v2:
 - reworded commit message and comment (Priyanka)

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig         |  3 +++
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h     | 15 +++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 24c606a232..046dcf539e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -45,6 +45,7 @@ config ARCH_LS1028A
        select SYS_FSL_ERRATUM_A008514 if !TFABOOT
        select SYS_FSL_ERRATUM_A009663 if !TFABOOT
        select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+       select SYS_FSL_ERRATUM_A050382
        imply PANIC_HANG
 
 config ARCH_LS1043A
@@ -584,6 +585,8 @@ config SYS_FSL_ERRATUM_A009660
 config SYS_FSL_ERRATUM_A009929
        bool
 
+config SYS_FSL_ERRATUM_A050382
+       bool
 
 config SYS_FSL_HAS_RGMII
        bool
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index 0b36416ad3..94ea99a349 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -105,7 +105,22 @@
 #define FSL_SEC_JR4_STREAM_ID          68
 
 #define FSL_SDMMC2_STREAM_ID           69
+
+/*
+ * Erratum A-050382 workaround
+ *
+ * Description:
+ *   The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not
+ *   correctly forwarded to the SMMU.
+ * Workaround:
+ *   Program eDMA ICID in the eDMA_AMQR register in DCFG to 40.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A050382
+#define FSL_EDMA_STREAM_ID             40
+#else
 #define FSL_EDMA_STREAM_ID             70
+#endif
+
 #define FSL_GPU_STREAM_ID              71
 #define FSL_DISPLAY_STREAM_ID          72
 #define FSL_SATA3_STREAM_ID            73
-- 
2.17.1

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