Turn on PCIe ECAM address range decoding on Q35.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
arch/x86/cpu/qemu/pci.c | 4 ++++
arch/x86/include/asm/arch-qemu/qemu.h | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c
index acbd922..2e94456 100644
--- a/arch/x86/cpu/qemu/pci.c
+++ b/arch/x86/cpu/qemu/pci.c
@@ -90,6 +90,10 @@ int board_pci_post_scan(struct pci_controller *hose)
xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
xbcs |= APIC_EN;
x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
+ } else {
+ /* Configure PCIe ECAM base address */
+ x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
+ CONFIG_PCIE_ECAM_BASE | BAR_EN);
}
/*
diff --git a/arch/x86/include/asm/arch-qemu/qemu.h
b/arch/x86/include/asm/arch-qemu/qemu.h
index 8c8e4ac..b67d342 100644
--- a/arch/x86/include/asm/arch-qemu/qemu.h
+++ b/arch/x86/include/asm/arch-qemu/qemu.h
@@ -22,6 +22,10 @@
#define IDE1_TIM 0x42
#define IDE_DECODE_EN (1 << 15)
+/* PCIe ECAM Base Address Register */
+#define PCIEX_BAR 0x60
+#define BAR_EN (1 << 0)
+
/* I/O Ports */
#define CMOS_ADDR_PORT 0x70
#define CMOS_DATA_PORT 0x71
--
1.8.2.1
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