Hi Bin,
On Sun, 3 Nov 2019 at 07:36, Simon Glass wrote:
>
> Hi Bin,
>
> On Sat, 2 Nov 2019 at 17:18, Bin Meng wrote:
> >
> > Hi Simon,
> >
> > On Sun, Nov 3, 2019 at 5:04 AM Simon Glass wrote:
> > >
> > > Hi Bin,
> > >
> > > On Fri, 1 Nov 2019 at 22:14, Bin Meng wrote:
> > > >
> > > > On Mon,
Hi Bin,
On Sat, 2 Nov 2019 at 17:18, Bin Meng wrote:
>
> Hi Simon,
>
> On Sun, Nov 3, 2019 at 5:04 AM Simon Glass wrote:
> >
> > Hi Bin,
> >
> > On Fri, 1 Nov 2019 at 22:14, Bin Meng wrote:
> > >
> > > On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> > > >
> > > > Most x86 CPUs use a
Hi Simon,
On Sun, Nov 3, 2019 at 5:04 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Fri, 1 Nov 2019 at 22:14, Bin Meng wrote:
> >
> > On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> > >
> > > Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
> > > top of 32-bit address
Hi Bin,
On Fri, 1 Nov 2019 at 22:14, Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
> > top of 32-bit address space, so that it can be executed in place and read
> > simply by copying from
On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
>
> Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
> top of 32-bit address space, so that it can be executed in place and read
> simply by copying from memory. For an 8MB ROM the mapping starts at
> 0xff80.
>
>
Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
top of 32-bit address space, so that it can be executed in place and read
simply by copying from memory. For an 8MB ROM the mapping starts at
0xff80.
However some recent Intel CPUs do not use a simple 1:1 memory map.
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