On Wed, Apr 5, 2017 at 5:29 AM, Fabio Estevam wrote:
> Hi Jagan,
>
> On Tue, Apr 4, 2017 at 2:27 PM, Jagan Teki wrote:
>
>> No, this isn't issue, just want to understand how you create reg init
>> in SPL in mx6q_dcd_table, means did you follow any order. because I'm
>> planning move *dl.cfg DCD t
Hi Jagan,
On Tue, Apr 4, 2017 at 2:27 PM, Jagan Teki wrote:
> No, this isn't issue, just want to understand how you create reg init
> in SPL in mx6q_dcd_table, means did you follow any order. because I'm
> planning move *dl.cfg DCD to SPL
Ok, got it. I thought you were asking about mx6qp sabrea
On Tue, Apr 4, 2017 at 9:20 PM, Fabio Estevam wrote:
> On Tue, Apr 4, 2017 at 12:47 PM, Jagan Teki wrote:
>> Any help?
>
> Sorry, didn't have time to look at this issue.
>
> At least SPL U-Boot boots fine in this board. Can you also try U-Boot
> from NXP and try to debug it?
No, this isn't issue
On Tue, Apr 4, 2017 at 12:47 PM, Jagan Teki wrote:
> Any help?
Sorry, didn't have time to look at this issue.
At least SPL U-Boot boots fine in this board. Can you also try U-Boot
from NXP and try to debug it?
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Any help?
On Wed, Mar 29, 2017 at 8:45 PM, Jagan Teki wrote:
> Hi Fabio,
>
> On Mon, Sep 26, 2016 at 5:44 PM, Fabio Estevam wrote:
>> From: Fabio Estevam
>>
>> When using SPL on i.mx6 we frequently notice some DDR initialization
>> mismatches between the SPL code and the non-SPL code.
>>
>> Thi
Hi Fabio,
On Mon, Sep 26, 2016 at 5:44 PM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> When using SPL on i.mx6 we frequently notice some DDR initialization
> mismatches between the SPL code and the non-SPL code.
>
> This causes stability issues like the ones reported at 7dbda25ecd6d7c
> ("mx6
From: Fabio Estevam
When using SPL on i.mx6 we frequently notice some DDR initialization
mismatches between the SPL code and the non-SPL code.
This causes stability issues like the ones reported at 7dbda25ecd6d7c
("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also:
http://lis
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