Re: [U-Boot] [PATCH v3 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

On 09/21/2016 04:25 AM, Chin Liang See wrote: > To enable configuration of sdr.ctrlcfg.extratime1 register which enable > extra clocks for read to write command timing. This is critical to > ensure successful LPDDR2 interface > > Signed-off-by: Chin Liang See > Cc: Marek Vasut > Cc: Dinh Nguyen

[U-Boot] [PATCH v3 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See Cc: Marek Vasut Cc: Dinh Nguyen --- Changes for v3 - Removed ifdef by setting macro to zero