On Mon, Dec 19, 2016 at 10:53:32AM +, Andre Przywara wrote:
> Hi,
>
> On 19/12/16 09:57, Maxime Ripard wrote:
> > On Mon, Dec 19, 2016 at 01:50:06AM +, Andre Przywara wrote:
> >> From: Jens Kuske
> >>
> >> So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as
> >> well) o
Hi,
On 19/12/16 09:57, Maxime Ripard wrote:
> On Mon, Dec 19, 2016 at 01:50:06AM +, Andre Przywara wrote:
>> From: Jens Kuske
>>
>> So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as
>> well) only applied coarse delay line settings, with one delay value for
>> all the data
On Mon, Dec 19, 2016 at 01:50:06AM +, Andre Przywara wrote:
> From: Jens Kuske
>
> So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as
> well) only applied coarse delay line settings, with one delay value for
> all the data lines in each byte lane and one value for the cont
From: Jens Kuske
So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as
well) only applied coarse delay line settings, with one delay value for
all the data lines in each byte lane and one value for the control lines.
Instead of setting the delays for whole bytes only allow setti
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