The LCDC assigned rate is 0, it will make boot error,
error log:"pll_para_config: the frequency can not be
0 Hz". Remove them, and the lcdc driver will do the
correct clock rate setting.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v3:
- New patch
Changes in v2: None
arch/arm/dts/rk3288.dtsi | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index da51878..2c8a616 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -604,19 +604,16 @@
u-boot,dm-pre-reloc;
#clock-cells = <1>;
#reset-cells = <1>;
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
- <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+ assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>, <&cru ACLK_CPU>,
<&cru HCLK_CPU>, <&cru PCLK_CPU>,
<&cru ACLK_PERI>, <&cru HCLK_PERI>,
<&cru PCLK_PERI>;
- assigned-clock-rates = <0>, <0>,
- <594000000>, <400000000>,
+ assigned-clock-rates = <594000000>, <400000000>,
<500000000>, <300000000>,
<150000000>, <75000000>,
<300000000>, <150000000>,
<75000000>;
- assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
};
grf: syscon@ff770000 {
--
2.7.4
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
