If you look at current board/freescale/p1_p2_rdb/law.c it doesn't have PCI
LAWs anymore. I think for your example you just need an empty data
structure:
struct law_entry law_table[] = {
};
this should hopefully make num_law_entries = 0;
+};
+
+int num_law_entries =
On Sat, Nov 12, 2011 at 12:16:05PM -0600, Kumar Gala wrote:
This entire file is identical to board/freescale/p1_p2_rdb/ddr.c. In
fact, since this board only boots via the On-Chip ROM, the whole file is
useless: fixed_sdram() should just return the RAM size. We're running
from RAM when
+phys_size_t fixed_sdram(void)
+{
+ char buf[32];
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ size_t ddr_size;
+ struct cpu_type *cpu;
+ ulong ddr_freq, ddr_freq_mhz;
+
+ cpu = gd-cpu;
+ /* P1020 and it's derivatives support max 32bit DDR width */
+ if (cpu-soc_ver ==
On Nov 10, 2011, at 3:11 PM, Ira W. Snyder wrote:
This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.
Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the
On Fri, Nov 11, 2011 at 07:22:14AM -0600, Kumar Gala wrote:
On Nov 10, 2011, at 3:11 PM, Ira W. Snyder wrote:
This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.
Unlike all other
On Fri, Nov 11, 2011 at 10:53 AM, Ira W. Snyder i...@ovro.caltech.edu wrote:
Does the board really support different DDR freq or is this copy / paste?
The memory is an SODIMM, but the RAM is configured before U-Boot runs by
the Freescale On-Chip ROM. See above comment.
If this is a P2020 you
On Fri, Nov 11, 2011 at 04:58:17PM +, McClintock Matthew-B29882 wrote:
On Fri, Nov 11, 2011 at 10:53 AM, Ira W. Snyder i...@ovro.caltech.edu wrote:
Does the board really support different DDR freq or is this copy / paste?
The memory is an SODIMM, but the RAM is configured before
On Fri, Nov 11, 2011 at 11:12 AM, Ira W. Snyder i...@ovro.caltech.edu wrote:
Yep, this is a P2020.
I'll check the Freescale documentation. Hopefully it provides an example
of how to configure the On-Chip ROM to use L2SRAM instead of DDR.
I'll try and find a U-Boot port that configures DDR
On Fri, Nov 11, 2011 at 08:36:47PM +, McClintock Matthew-B29882 wrote:
On Fri, Nov 11, 2011 at 11:12 AM, Ira W. Snyder i...@ovro.caltech.edu wrote:
Yep, this is a P2020.
I'll check the Freescale documentation. Hopefully it provides an example
of how to configure the On-Chip ROM to use
On Fri, Nov 11, 2011 at 3:03 PM, Ira W. Snyder i...@ovro.caltech.edu wrote:
Thanks. That config_sram.dat is exactly what I came up with.
I have my board booting via L2SRAM, but the DDR doesn't get configured
correctly yet. I'm trying to figure out how the DDR SPD stuff works in
U-Boot. I've
On Fri, Nov 11, 2011 at 09:07:23PM +, McClintock Matthew-B29882 wrote:
On Fri, Nov 11, 2011 at 3:03 PM, Ira W. Snyder i...@ovro.caltech.edu wrote:
Thanks. That config_sram.dat is exactly what I came up with.
I have my board booting via L2SRAM, but the DDR doesn't get configured
Adding York who might be able to help more...
-M
On Fri, Nov 11, 2011 at 4:18 PM, Ira W. Snyder i...@ovro.caltech.edu wrote:
On Fri, Nov 11, 2011 at 09:07:23PM +, McClintock Matthew-B29882 wrote:
On Fri, Nov 11, 2011 at 3:03 PM, Ira W. Snyder i...@ovro.caltech.edu wrote:
Thanks. That
Looking good so far, what's the question? You can always override the
register values and try it since you got the interactive debug up.
York
On Fri, 2011-11-11 at 14:54 -0800, McClintock Matthew-B29882 wrote:
Adding York who might be able to help more...
-M
On Fri, Nov 11, 2011 at 4:18
On Fri, Nov 11, 2011 at 03:02:46PM -0800, York Sun wrote:
Looking good so far, what's the question? You can always override the
register values and try it since you got the interactive debug up.
Well, it doesn't work out of the box.
I'm very worried about the following messages:
unknown
On Fri, Nov 11, 2011 at 03:10:43PM -0800, Ira W. Snyder wrote:
On Fri, Nov 11, 2011 at 03:02:46PM -0800, York Sun wrote:
Looking good so far, what's the question? You can always override the
register values and try it since you got the interactive debug up.
Well, it doesn't work out of
This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.
Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the HRESET_REQ register does not work.
This board has no NOR
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