From: Chao Fu <b44...@freescale.com>
Enable DSPI iomux for vf610twr board.
Add the SPI configuration for vf610twr board.
Signed-off-by: Chao Fu <b44...@freescale.com>
---
Change in v2 :
New.
Change in v3 :
None.
board/freescale/vf610twr/vf610twr.c | 15 ++++++++++++++-
include/configs/vf610twr.h | 15 +++++++++++++++
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/board/freescale/vf610twr/vf610twr.c
b/board/freescale/vf610twr/vf610twr.c
index 699ea7f..ee6612f 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -278,6 +278,18 @@ static void setup_iomux_i2c(void)
imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
}
+static void setup_iomux_dspi(void)
+{
+ static const iomux_v3_cfg_t dspi0_pads[] = {
+ VF610_PAD_PTB19__DSPI0_CS0,
+ VF610_PAD_PTB20__DSPI0_SIN,
+ VF610_PAD_PTB21__DSPI0_SOUT,
+ VF610_PAD_PTB22__DSPI0_SCK,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(dspi0_pads, ARRAY_SIZE(dspi0_pads));
+}
+
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{ESDHC1_BASE_ADDR},
@@ -315,7 +327,7 @@ static void clock_init(void)
struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
- CCM_CCGR0_UART1_CTRL_MASK);
+ CCM_CCGR0_UART1_CTRL_MASK | CCM_CCGR0_DSPI0_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
@@ -386,6 +398,7 @@ int board_early_init_f(void)
setup_iomux_uart();
setup_iomux_enet();
setup_iomux_i2c();
+ setup_iomux_dspi();
return 0;
}
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 8d0a00d..73f96e7 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -74,6 +74,21 @@
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_SPD_BUS_NUM 0
+/* DSPI Configs */
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define MMAP_DSPI SPI0_BASE_ADDR
+#define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
+ DSPI_CTAR_PCSSCK_1CLK | \
+ DSPI_CTAR_PASC(0) | \
+ DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | \
+ DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(0))
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_LOADADDR 0x82000000
--
1.8.4
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