Currently the sd_change_freq function allocates two buffers on the
stack that it passes down to the MMC device driver. These buffers
could be unaligned to the L1 dcache line size. This causes problems
when using DMA and with caches enabled.
This patch correctly cache alignes the buffers used for
built fine for me
Acked-by: Mike Frysinger
-mike
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Dear Anton Staaf,
In message <1318463764-28244-4-git-send-email-robot...@chromium.org> you wrote:
> Currently the sd_change_freq function allocates two buffers on the
> stack that it passes down to the MMC device driver. These buffers
> could be unaligned to the L1 dcache line size. This causes
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