Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0.
Signed-off-by: Chin Liang See <cl...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Dinh Nguyen <dingu...@opensource.altera.com> --- Changes for v3 - Add macro for all boards to avoid ifdef --- board/ebv/socrates/qts/sdram_config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h index cf9d1d3..b4872c2 100644 --- a/board/ebv/socrates/qts/sdram_config.h +++ b/board/ebv/socrates/qts/sdram_config.h @@ -49,6 +49,9 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -- 2.2.2 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
