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On 08/27/2013 05:51 AM, Andre Przywara wrote:
> On 08/27/2013 02:23 AM, Masahiro Yamada wrote:
>> Hello Andre,
>>
>>> +/* the vector table for secure state */ +_monitor_vectors: +
>>> .word 0/* reset */ +.word 0 /* undef */ +adr pc,
>>> _s
On 08/27/2013 02:23 AM, Masahiro Yamada wrote:
Hello Andre,
+/* the vector table for secure state */
+_monitor_vectors:
+ .word 0 /* reset */
+ .word 0 /* undef */
+ adr pc, _secure_monitor
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+
Hello Andre,
> +/* the vector table for secure state */
> +_monitor_vectors:
> + .word 0 /* reset */
> + .word 0 /* undef */
> + adr pc, _secure_monitor
> + .word 0
> + .word 0
> + .word 0
> + .word 0
> + .word 0
> + .word 0 /* pad */
Could you explain why the
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM archite
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