On 4/16/19 10:04 PM, Simon Goldschmidt wrote:
> To clean up reset handling for socfpga gen5, port the DDR driver to DM
> using UCLASS_RAM and implement proper reset handling.
>
> This gets us rid of one ad-hoc call to socfpga_per_reset().
>
> The gen5 driver is implemented in 2 distinct files. On
To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.
This gets us rid of one ad-hoc call to socfpga_per_reset().
The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touch
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