On 06/01/2019 19:22, Jagan Teki wrote:
> On Sun, Jan 6, 2019 at 6:49 PM André Przywara wrote:
>>
>> On 31/12/2018 16:59, Jagan Teki wrote:
>>
>> Hi Jagan,
>>
>> many thanks for picking this up, I was about to come back to this
>> myself. I am looking at the pinctrl part at the moment, so good you
On Sun, Jan 6, 2019 at 6:49 PM André Przywara wrote:
>
> On 31/12/2018 16:59, Jagan Teki wrote:
>
> Hi Jagan,
>
> many thanks for picking this up, I was about to come back to this
> myself. I am looking at the pinctrl part at the moment, so good you are
> working on the clocks!
>
> TL;DR: I am
On 31/12/2018 16:59, Jagan Teki wrote:
Hi Jagan,
many thanks for picking this up, I was about to come back to this
myself. I am looking at the pinctrl part at the moment, so good you are
working on the clocks!
TL;DR: I am good with the first patches, but would like to drop the last
five 5
On Mon, Dec 31, 2018 at 10:30 PM Jagan Teki wrote:
>
> Although the previous version[1] is properly handled the clock gates
> with enable and disable management, but this series is trying to add
> some more complex Allwinner CLK architecture by handling parent clock
> and other CLK attributes.
>
Although the previous version[1] is properly handled the clock gates
with enable and disable management, but this series is trying to add
some more complex Allwinner CLK architecture by handling parent clock
and other CLK attributes.
Allwinner Clock control unit comprises of parent clocks, gates,
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