Re: [U-Boot] [PATCH v5 3/5] spi: cadence_qspi: fix base trigger address transfer start address

Hi, -Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Thursday, August 27, 2015 1:40 AM To: Vikas MANOCHA Cc: u-boot@lists.denx.de; s...@denx.de; grmo...@opensource.altera.com; jt...@openedev.com Subject: Re: [PATCH v5 3/5] spi: cadence_qspi: fix base trigger

Re: [U-Boot] [PATCH v5 3/5] spi: cadence_qspi: fix base trigger address transfer start address

On Thursday, August 27, 2015 at 12:44:28 AM, Vikas Manocha wrote: This patch is to separate the base trigger from the read/write transfer start addresses. Base trigger register address (0x1c register) corresponds to the address which should be put on AHB bus to handle indirect transfer

[U-Boot] [PATCH v5 3/5] spi: cadence_qspi: fix base trigger address transfer start address

This patch is to separate the base trigger from the read/write transfer start addresses. Base trigger register address (0x1c register) corresponds to the address which should be put on AHB bus to handle indirect transfer triggered before. To handle indirect transfer we need to issue addresses