Hi Marek/Tom,
As I understood correctly.
I would merge my changes in "denx-uboot-arm/master" as
"u-boot-tegra/master", where actually I tested my patch, is
pulled in "denx-uboot-arm/master".
Will that work...
Thanks & Regards,
Puneet
On Monday 02 April 2012 10:02 PM, Marek Vasut wrote:
Dear
Dear Tom Warren,
> Marek,
>
> > -Original Message-
> > From: Marek Vasut [mailto:ma...@denx.de]
> > Sent: Monday, April 02, 2012 9:12 AM
> > To: Tom Warren
> > Cc: Puneet Saxena; Mike Frysinger; u-boot@lists.denx.de;
> > s...@chromium.org; li...@bohmer.net; tr...@ti.com;
> > albert.u.b...
Marek,
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Monday, April 02, 2012 9:12 AM
> To: Tom Warren
> Cc: Puneet Saxena; Mike Frysinger; u-boot@lists.denx.de; s...@chromium.org;
> li...@bohmer.net; tr...@ti.com; albert.u.b...@aribaud.net
> Subject: Re: [PATCH v8]
Dear Tom Warren,
> Marek, Puneet, et al.,
>
> > -Original Message-
> > From: Marek Vasut [mailto:ma...@denx.de]
> > Sent: Monday, March 19, 2012 8:47 AM
> > To: Tom Warren
> > Cc: Puneet Saxena; Mike Frysinger; u-boot@lists.denx.de;
> > s...@chromium.org; li...@bohmer.net; tr...@ti.com;
>
Marek, Puneet, et al.,
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Monday, March 19, 2012 8:47 AM
> To: Tom Warren
> Cc: Puneet Saxena; Mike Frysinger; u-boot@lists.denx.de; s...@chromium.org;
> li...@bohmer.net; tr...@ti.com; albert.u.b...@aribaud.net
> Subject
Dear Tom Warren,
> Marek,
>
> > -Original Message-
> > From: Marek Vasut [mailto:marek.va...@gmail.com]
> > Sent: Monday, March 19, 2012 7:43 AM
> > To: Puneet Saxena
> > Cc: Mike Frysinger; u-boot@lists.denx.de; s...@chromium.org;
> > li...@bohmer.net; tr...@ti.com; Tom Warren
> > Subjec
Marek,
> -Original Message-
> From: Marek Vasut [mailto:marek.va...@gmail.com]
> Sent: Monday, March 19, 2012 7:43 AM
> To: Puneet Saxena
> Cc: Mike Frysinger; u-boot@lists.denx.de; s...@chromium.org;
> li...@bohmer.net; tr...@ti.com; Tom Warren
> Subject: Re: [PATCH v8] usb: align buffers
Dear Puneet Saxena,
> Hi Marek,
> I adapted my patch for git://git.denx.de/u-boot-usb.git master branch.
> As the build for target "Seaboard" is broken once I enable USB in
> Seaboard.h,
> I am unable to test my changes on "u-boot-usb".
u-boot-usb is forked off the mainline u-boot.git ... tegra s
Hi Marek,
I adapted my patch for git://git.denx.de/u-boot-usb.git master branch.
As the build for target "Seaboard" is broken once I enable USB in
Seaboard.h,
I am unable to test my changes on "u-boot-usb".
I would have to merge lots of changes from "denx-uboot-tegra" to make it
working for "u-
Dear Puneet Saxena,
I hope you found the rebased patch I attached useful.
> Hi Marek,
> I need to remove the changes in ehci_hcd.c as per Mike's comment and
> adapt my patch for git://git.denx.de/u-boot-usb.git master branch.
> So will be sending next patch with the above changes, shortly.
Let m
Hi Marek,
I need to remove the changes in ehci_hcd.c as per Mike's comment and
adapt my patch for git://git.denx.de/u-boot-usb.git master branch.
So will be sending next patch with the above changes, shortly.
With this resultant patch we see warnings for few start address
warnings(related to e
Dear Puneet Saxena,
What's the development on this patch? I gave it a run (find attachment, I
rebased it), but it doesn't work (alignment issues in ehci_hcd). Even if I
added
a bounce buffer, it still didn't work :-(
Best regards,
Marek Vasut
From a907a498a9689aa9706f9ff76f0428a9941a4a7a Mon S
Dear Mike Frysinger,
> On Wednesday 07 March 2012 02:12:22 puneets wrote:
> > On Tuesday 06 March 2012 08:37 AM, Mike Frysinger wrote:
> > >> --- a/drivers/usb/host/ehci-hcd.c
> > >> +++ b/drivers/usb/host/ehci-hcd.c
> > >>
> > >> static void flush_invalidate(u32 addr, int size, int flush)
> >
On Wednesday 07 March 2012 02:12:22 puneets wrote:
> On Tuesday 06 March 2012 08:37 AM, Mike Frysinger wrote:
> >> --- a/drivers/usb/host/ehci-hcd.c
> >> +++ b/drivers/usb/host/ehci-hcd.c
> >>
> >> static void flush_invalidate(u32 addr, int size, int flush)
> >> {
> >> + /*
> >> + * Size is
Dear puneets,
> Hi Marek,
>
> On Thursday 08 March 2012 07:42 PM, Marek Vasut wrote:
> > Dear puneets,
> >
> >> Hi Marek,
> >>
> >> On Thursday 08 March 2012 03:36 AM, Marek Vasut wrote:
> >>> Dear puneets,
> >>>
> Hi Mike,
>
> On Tuesday 06 March 2012 08:37 AM, Mike Frysinger
Hi Marek,
On Thursday 08 March 2012 07:42 PM, Marek Vasut wrote:
Dear puneets,
Hi Marek,
On Thursday 08 March 2012 03:36 AM, Marek Vasut wrote:
Dear puneets,
Hi Mike,
On Tuesday 06 March 2012 08:37 AM, Mike Frysinger wrote:
* PGP Signed by an unknown key
On Monday 05 March 2012 09:46:21
Dear puneets,
> Hi Marek,
>
> On Thursday 08 March 2012 03:36 AM, Marek Vasut wrote:
> > Dear puneets,
> >
> >> Hi Mike,
> >>
> >> On Tuesday 06 March 2012 08:37 AM, Mike Frysinger wrote:
> >>> * PGP Signed by an unknown key
> >>>
> >>> On Monday 05 March 2012 09:46:21 Puneet Saxena wrote:
> >
Hi Marek,
On Thursday 08 March 2012 03:36 AM, Marek Vasut wrote:
Dear puneets,
Hi Mike,
On Tuesday 06 March 2012 08:37 AM, Mike Frysinger wrote:
* PGP Signed by an unknown key
On Monday 05 March 2012 09:46:21 Puneet Saxena wrote:
As DMA expects the buffers to be equal and larger then
cache
Dear puneets,
> Hi Mike,
>
> On Tuesday 06 March 2012 08:37 AM, Mike Frysinger wrote:
> > * PGP Signed by an unknown key
> >
> > On Monday 05 March 2012 09:46:21 Puneet Saxena wrote:
> >> As DMA expects the buffers to be equal and larger then
> >> cache lines, This aligns buffers at cacheline.
>
Hi Mike,
Forgot to write the link in below mail.
Here is the link:
http://lists.denx.de/pipermail/u-boot/2011-December/112138.html
Do you want me to show a warning where I am making size as cacheline size?
Thanx & Regards,,
Puneet
On Wednesday 07 March 2012 12:42 PM, puneets wrote:
Hi Mike,
On
Hi Mike,
On Tuesday 06 March 2012 08:37 AM, Mike Frysinger wrote:
* PGP Signed by an unknown key
On Monday 05 March 2012 09:46:21 Puneet Saxena wrote:
As DMA expects the buffers to be equal and larger then
cache lines, This aligns buffers at cacheline.
i don't think this statement is true. DM
Dear Puneet Saxena,
> Hi Simon,
> I do see only first warning on all the devices and rest of the warnings
> on a few mass storage device.
>
> My patch fixing these warnings is not accepted. Please see below link
> for further info -
>
> http://lists.denx.de/pipermail/u-boot/2012-March/119404.htm
Hi Simon,
I do see only first warning on all the devices and rest of the warnings
on a few mass storage device.
My patch fixing these warnings is not accepted. Please see below link
for further info -
http://lists.denx.de/pipermail/u-boot/2012-March/119404.html
IMO, these warnings spew when w
On Monday 05 March 2012 09:46:21 Puneet Saxena wrote:
> As DMA expects the buffers to be equal and larger then
> cache lines, This aligns buffers at cacheline.
i don't think this statement is true. DMA doesn't care about alignment (well,
some do, but it's not related to cache lines but rather so
> Dear Simon Glass,
>
> > Hi Puneet,
> >
> > On Mon, Mar 5, 2012 at 6:46 AM, Puneet Saxena wrote:
> > > As DMA expects the buffers to be equal and larger then
> > > cache lines, This aligns buffers at cacheline.
> > >
> > > Signed-off-by: Puneet Saxena
> >
> > Tested on Seaboard:
> >
> > Tes
Dear Simon Glass,
> Hi Puneet,
>
> On Mon, Mar 5, 2012 at 6:46 AM, Puneet Saxena wrote:
> > As DMA expects the buffers to be equal and larger then
> > cache lines, This aligns buffers at cacheline.
> >
> > Signed-off-by: Puneet Saxena
>
> Tested on Seaboard:
>
> Tested-by: Simon Glass
> Ack
Hi Puneet,
On Mon, Mar 5, 2012 at 6:46 AM, Puneet Saxena wrote:
> As DMA expects the buffers to be equal and larger then
> cache lines, This aligns buffers at cacheline.
>
> Signed-off-by: Puneet Saxena
Tested on Seaboard:
Tested-by: Simon Glass
Acked-by: Simon Glass
I do still see a few al
Dear Puneet Saxena,
I replaced the old patch with this one. Thanks!
> As DMA expects the buffers to be equal and larger then
> cache lines, This aligns buffers at cacheline.
>
> Signed-off-by: Puneet Saxena
> ---
>
> Changes for V7:
> - Trivial change, missed removing memcpy. Removed now.
As DMA expects the buffers to be equal and larger then
cache lines, This aligns buffers at cacheline.
Signed-off-by: Puneet Saxena
---
Changes for V7:
- Trivial change, missed removing memcpy. Removed now.
Changes for V8:
- Corrected "setup_packet" allocation using "ALLOC_CACHE_ALIGN_BUF
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