On Thu, 2019-02-14 at 17:26 +0100, Marek Vasut wrote:
> On 2/14/19 4:47 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 16:13 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
On Thu, 2019-02-14 at 17:26 +0100, Marek Vasut wrote:
> On 2/14/19 4:47 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 16:13 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
On 2/14/19 4:47 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 16:13 +0100, Marek Vasut wrote:
>> On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
>
>
> On Thu, 2019-02-14
On Thu, 2019-02-14 at 16:13 +0100, Marek Vasut wrote:
> On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-02-14 at 11:35 +0100, Marek Vasut wrote:
On 2/14/19 4:11 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
>> On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 11:35 +0100, Marek Vasut wrote:
On 2/14/19 7:04 AM, Chee, Tien Fong wrote:
>
>
> On Thu, 2019-02-14
On Thu, 2019-02-14 at 13:24 +0100, Marek Vasut wrote:
> On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 11:35 +0100, Marek Vasut wrote:
> > >
> > > On 2/14/19 7:04 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-02-14 at 00:04 +0100, Marek Vasut wrote:
On 2/14/19 12:23 PM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 11:35 +0100, Marek Vasut wrote:
>> On 2/14/19 7:04 AM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-02-14 at 00:04 +0100, Marek Vasut wrote:
On 2/13/19 11:45 PM, Dalon L Westergreen wrote:
>
>
> On Wed,
On Thu, 2019-02-14 at 11:35 +0100, Marek Vasut wrote:
> On 2/14/19 7:04 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-02-14 at 00:04 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 11:45 PM, Dalon L Westergreen wrote:
> > > >
> > > >
> > > > On Wed, 2019-02-13 at 17:10 +0100, Marek Vasut
On 2/14/19 7:04 AM, Chee, Tien Fong wrote:
> On Thu, 2019-02-14 at 00:04 +0100, Marek Vasut wrote:
>> On 2/13/19 11:45 PM, Dalon L Westergreen wrote:
>>>
>>> On Wed, 2019-02-13 at 17:10 +0100, Marek Vasut wrote:
On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
>
> From: Tien
On Thu, 2019-02-14 at 00:04 +0100, Marek Vasut wrote:
> On 2/13/19 11:45 PM, Dalon L Westergreen wrote:
> >
> > On Wed, 2019-02-13 at 17:10 +0100, Marek Vasut wrote:
> > >
> > > On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > > Add
On 2/13/19 11:45 PM, Dalon L Westergreen wrote:
> On Wed, 2019-02-13 at 17:10 +0100, Marek Vasut wrote:
>> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
>>> From: Tien Fong Chee
>>>
>>> Add default fitImage file bundling FPGA bitstreams for Arria10.
>>>
>>> Signed-off-by: Tien Fong Chee
On Wed, 2019-02-13 at 17:10 +0100, Marek Vasut wrote:
> On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> > From: Tien Fong Chee
> >
> > Add default fitImage file bundling FPGA bitstreams for Arria10.
> >
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> >
> > changes for v8
> > - Changed
On 2/13/19 3:18 PM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add default fitImage file bundling FPGA bitstreams for Arria10.
>
> Signed-off-by: Tien Fong Chee
>
> ---
>
> changes for v8
> - Changed the FPGA node name to fpga-core and fpga-periph for both core and
> periph
From: Tien Fong Chee
Add default fitImage file bundling FPGA bitstreams for Arria10.
Signed-off-by: Tien Fong Chee
---
changes for v8
- Changed the FPGA node name to fpga-core and fpga-periph for both core and
periph bitstreams respectively.
---
board/altera/arria10-socdk/fit_spl_fpga.its
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