On Monday, February 23, 2015 at 06:00:45 PM, Dinh Nguyen wrote:
> On 2/23/15 10:57 AM, Marek Vasut wrote:
> > On Monday, February 23, 2015 at 05:39:53 PM, Dinh Nguyen wrote:
> >> On 2/23/15 10:37 AM, Dinh Nguyen wrote:
> >>> On 2/15/15 5:25 PM, Pavel Machek wrote:
> Hi!
>
> > +#if EN
On 2/23/15 10:57 AM, Marek Vasut wrote:
> On Monday, February 23, 2015 at 05:39:53 PM, Dinh Nguyen wrote:
>> On 2/23/15 10:37 AM, Dinh Nguyen wrote:
>>> On 2/15/15 5:25 PM, Pavel Machek wrote:
Hi!
> +#if ENABLE_BRINGUP_DEBUGGING
Could we get rid of this for initial merge?
Hi!
> +#if ENABLE_BRINGUP_DEBUGGING
Could we get rid of this for initial merge?
> +static inline void reg_file_set_sub_stage(uint32_t set_sub_stage)
> +{
> + /* Read the current group and stage */
> + uint32_t cur_stage_group = IORD_32DIRECT(REG_FILE_CUR_STAGE, 0);
Could normal u-boot m
Hi!
> From: Dinh Nguyen
>
> This adds the code to configure the SDRAM controller that is found in the
> SoCFGPA Cyclone5 and Arria5 platforms.
>
> Signed-off-by: Dinh Nguyen
> +/**
> +
> *
On Sat 2015-01-17 03:39:46, Marek Vasut wrote:
> On Friday, January 16, 2015 at 08:04:20 PM, Pavel Machek wrote:
> > Hi!
>
> Hi!
>
> > > > +void wait_di_buffer(void)
> > > > +{
> > > > + if (debug_data->di_report.cur_samples == NUM_DI_SAMPLE) {
> > > > + debug_data->di_report.
On 21.01.2015 00:51, Dinh Nguyen wrote:
On 01/14/2015 05:34 PM, Marek Vasut wrote:
On Wednesday, January 14, 2015 at 05:40:41 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen
Hi!
This adds the code to configure the SDRAM controller that is found in the
SoCFGPA Cyclone5 and Arria
On 01/14/2015 05:34 PM, Marek Vasut wrote:
> On Wednesday, January 14, 2015 at 05:40:41 PM, dingu...@opensource.altera.com
> wrote:
>> From: Dinh Nguyen
>
> Hi!
>
>> This adds the code to configure the SDRAM controller that is found in the
>> SoCFGPA Cyclone5 and Arria5 platforms.
>>
>> Signed-
On Friday, January 16, 2015 at 08:04:20 PM, Pavel Machek wrote:
> Hi!
Hi!
> > > +void wait_di_buffer(void)
> > > +{
> > > + if (debug_data->di_report.cur_samples == NUM_DI_SAMPLE) {
> > > + debug_data->di_report.flags |= DI_REPORT_FLAGS_READY;
> > > + while (debug_data->di_report.
Hi!
> > +void wait_di_buffer(void)
> > +{
> > + if (debug_data->di_report.cur_samples == NUM_DI_SAMPLE) {
> > + debug_data->di_report.flags |= DI_REPORT_FLAGS_READY;
> > + while (debug_data->di_report.cur_samples != 0)
> > + ;
>
> Please get rid of such end
On Wednesday, January 14, 2015 at 05:40:41 PM, dingu...@opensource.altera.com
wrote:
> From: Dinh Nguyen
Hi!
> This adds the code to configure the SDRAM controller that is found in the
> SoCFGPA Cyclone5 and Arria5 platforms.
>
> Signed-off-by: Dinh Nguyen
> ---
> arch/arm/cpu/armv7/socfpga/
10 matches
Mail list logo