Re: [U-Boot] [Patch v3] driver/ddr/fsl: Fix MRC_CYC calculation for DDR3

On 12/02/2014 11:18 AM, York Sun wrote: > For DDR controller version 4.7 or newer, MRC_CYC (mode register set > cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD > is max(12nCK, 15ns) according to JEDEC spec. > > DDR4 is not affected by this change. > > Signed-off-by: York Sun

[U-Boot] [Patch v3] driver/ddr/fsl: Fix MRC_CYC calculation for DDR3

For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun --- Change log v3: Add cast for using max() v2: Appl