This series adds a Kconfig to disable cache maintenance operations on a coherent architectures. And disable cache flush/invalidate ops for SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent)
Vignesh Raghavendra (2): arch: armv8: Provide a way to disable cache maintenance ops board: ti: am654: select SYS_ARCH_IS_COHERENT for arm64 arch/Kconfig | 7 +++++++ arch/arm/cpu/armv8/cache_v8.c | 18 ++++++++++++++++++ board/ti/am65x/Kconfig | 1 + 3 files changed, 26 insertions(+) -- 2.21.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
