Support SPMI arbiter on Qualcomm Snapdragon devices.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikow...@gmail.com>
---
drivers/spmi/Kconfig | 6 ++
drivers/spmi/Makefile | 1 +
drivers/spmi/spmi-msm.c | 183 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 190 insertions(+)
create mode 100644 drivers/spmi/spmi-msm.c
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index 2d8d78b..4f17df0 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -7,4 +7,10 @@ config DM_SPMI
Select this to enable to support SPMI bus.
SPMI (System Power Management Interface) bus is used
to connect PMIC devices on various SoCs.
+
+config SPMI_MSM
+ boolean "Support Qualcomm SPMI bus"
+ depends on DM_SPMI
+ ---help---
+ Support SPMI implementation found on Qualcomm Snapdragon SoCs.
endmenu
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
index 2015b1a..419fe1d 100644
--- a/drivers/spmi/Makefile
+++ b/drivers/spmi/Makefile
@@ -5,3 +5,4 @@
#
obj-$(CONFIG_DM_SPMI) += spmi-uclass.o
+obj-$(CONFIG_SPMI_MSM) += spmi-msm.o
diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c
new file mode 100644
index 0000000..6781a92
--- /dev/null
+++ b/drivers/spmi/spmi-msm.c
@@ -0,0 +1,183 @@
+/*
+ * Qualcomm SPMI bus driver
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikow...@gmail.com>
+ *
+ * Loosely based on Little Kernel driver
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <spmi/spmi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARB_CHANNEL_OFFSET(n) (0x800 + 0x4 * (n))
+#define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
+
+#define SPMI_REG_CMD0 0x0
+#define SPMI_REG_CONFIG 0x4
+#define SPMI_REG_STATUS 0x8
+#define SPMI_REG_WDATA 0x10
+#define SPMI_REG_RDATA 0x18
+
+#define SPMI_CMD_OPCODE_SHIFT 27
+#define SPMI_CMD_SLAVE_ID_SHIFT 20
+#define SPMI_CMD_ADDR_SHIFT 12
+#define SPMI_CMD_ADDR_OFFSET_SHIFT 4
+#define SPMI_CMD_BYTE_CNT_SHIFT 0
+
+#define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
+#define SPMI_CMD_EXT_REG_READ_LONG 0x01
+
+#define SPMI_STATUS_DONE 0x1
+
+#define SPMI_MAX_CHANNELS 128
+#define SPMI_MAX_SLAVES 16
+#define SPMI_MAX_PERIPH 256
+
+struct msm_spmi_priv {
+ phys_addr_t arb_core; /* ARB Core base */
+ phys_addr_t spmi_core; /* SPMI core */
+ phys_addr_t spmi_obs; /* SPMI observer */
+ /* SPMI channel map */
+ uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
+};
+
+static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
+ uint8_t val)
+{
+ struct msm_spmi_priv *p = dev_get_priv(dev);
+ unsigned channel;
+ uint32_t reg = 0;
+
+ if (usid >= SPMI_MAX_SLAVES)
+ return -EIO;
+ if (pid >= SPMI_MAX_PERIPH)
+ return -EIO;
+
+ channel = p->channel_map[usid][pid];
+
+ /* Disable IRQ mode for the current channel*/
+ writel(0x0, p->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
+
+ /* Write single byte */
+ writel(val, p->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
+
+ /* Prepare write command */
+ reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
+ reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
+ reg |= (pid << SPMI_CMD_ADDR_SHIFT);
+ reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
+ reg |= 1; /* byte count */
+
+ /* Send write command */
+ writel(reg, p->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+
+ /* Wait till CMD DONE status */
+ reg = 0;
+ while (!reg) {
+ reg = readl(p->spmi_core + SPMI_CH_OFFSET(channel) +
+ SPMI_REG_STATUS);
+ }
+
+ if (reg ^ SPMI_STATUS_DONE) {
+ printf("SPMI write failure.\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off)
+{
+ struct msm_spmi_priv *p = dev_get_priv(dev);
+ unsigned channel;
+ uint32_t reg = 0;
+
+ if (usid >= SPMI_MAX_SLAVES)
+ return -EIO;
+ if (pid >= SPMI_MAX_PERIPH)
+ return -EIO;
+
+ channel = p->channel_map[usid][pid];
+
+ /* Disable IRQ mode for the current channel*/
+ writel(0x0, p->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
+
+ /* Prepare read command */
+ reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
+ reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
+ reg |= (pid << SPMI_CMD_ADDR_SHIFT);
+ reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
+ reg |= 1; /* byte count */
+
+ /* Request read */
+ writel(reg, p->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
+
+ /* Wait till CMD DONE status */
+ reg = 0;
+ while (!reg) {
+ reg = readl(p->spmi_obs + SPMI_CH_OFFSET(channel) +
+ SPMI_REG_STATUS);
+ }
+
+ if (reg ^ SPMI_STATUS_DONE) {
+ printf("SPMI read failure.\n");
+ return -EIO;
+ }
+
+ /* Read the data */
+ return readl(p->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_RDATA) &
+ 0xFF;
+}
+
+static struct dm_spmi_ops msm_spmi_ops = {
+ .read = msm_spmi_read,
+ .write = msm_spmi_write,
+};
+
+static int msm_spmi_probe(struct udevice *dev)
+{
+ struct msm_spmi_priv *priv = dev_get_priv(dev);
+ int i;
+
+ priv->arb_core = dev_get_addr(dev);
+ priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+
dev->parent->of_offset,
+ dev->of_offset,
"reg",
+ 1, NULL);
+ priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+
dev->parent->of_offset,
+ dev->of_offset, "reg",
+ 2, NULL);
+
+ /* Scan peripherals connected to each SPMI channel */
+ for (i = 0; i < SPMI_MAX_CHANNELS ; i++) {
+ uint32_t periph = readl(priv->arb_core + ARB_CHANNEL_OFFSET(i));
+ uint8_t slave_id = (periph & 0xf0000) >> 16;
+ uint8_t pid = (periph & 0xff00) >> 8;
+
+ priv->channel_map[slave_id][pid] = i;
+ }
+ return 0;
+}
+
+static const struct udevice_id msm_spmi_ids[] = {
+ { .compatible = "qcom,spmi-pmic-arb" },
+ { }
+};
+
+U_BOOT_DRIVER(msm_spmi) = {
+ .name = "msm_spmi",
+ .id = UCLASS_SPMI,
+ .of_match = msm_spmi_ids,
+ .ops = &msm_spmi_ops,
+ .probe = msm_spmi_probe,
+ .priv_auto_alloc_size = sizeof(struct msm_spmi_priv),
+};
--
2.5.0
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