Hi
On 01/20/2017 12:17 AM, Adam Ford wrote:
> On the OMAP36xx/37xx the CONTROL_WKUP_CTRL register has
> a field (bit 6) named GPIO_IO_PWRDNZ. If 0, the IO buffers which
> are related to GPIO_126, 127 and 129 are disabled. Some boards may
> need this for MMC. After the PBIAS is configured, this bi
On the OMAP36xx/37xx the CONTROL_WKUP_CTRL register has
a field (bit 6) named GPIO_IO_PWRDNZ. If 0, the IO buffers which
are related to GPIO_126, 127 and 129 are disabled. Some boards may
need this for MMC. After the PBIAS is configured, this bit should
be set high to enable these GPIO pins.
V3:
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