On Thu, Jun 04, 2015 at 04:42:36PM +0530, Lokesh Vutla wrote: > On DRA7, in addition to the regular muxing of pins, an additional > hardware module called IODelay which is also expected to be > configured. This "IODelay" module has it's own register space that is > independent of the control module. > > It is advocated strongly in TI's official documentation considering > the existing design of the DRA7 family of processors during mux or > IODelay recalibration, there is a potential for a significant glitch > which may cause functional impairment to certain hardware. It is > hence recommended to do muxing as part of IOdelay recalibration. > > IODELAY recalibration sequence: > - Complete AVS voltage change on VDD_CORE_L > - Unlock IODLAY config registers. > - Perform IO delay calibration with predefined values. > - Isolate all the IOs > - Update the delay mechanism for each IO with new calibrated values. > - Configure PAD configuration registers > - De-isolate all the IOs. > - Relock IODELAY config registers. > > Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com> > Signed-off-by: Nishanth Menon <n...@ti.com>
Applied to u-boot/master, thanks! -- Tom
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