From: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikar...@microchip.com>

add device tree files for sam9x60ek board with below changes.

- Add initial device nodes (pmc, pinctrl, sdhc, dbgu & pit)
- Add the reg property for the pinctrl node.
- Add the "u-boot,dm-pre-reloc" property to determine which nodes
  are used by the board_init_f stage.

Signed-off-by: Sandeep Sheriker Mallikarjun 
<sandeepsheriker.mallikar...@microchip.com>
[prasanthi.chellaku...@microchip.com: fix style/whitespace issues]
Signed-off-by: Prasanthi Chellakumar <prasanthi.chellaku...@microchip.com>
[nicolas.fe...@microchip.com:
- fix gclk,
- fix pio/pinctrl controller definition and allow to have more
  than only PIOA for this SoC,
- removing pinctrl address]
Signed-off-by: Nicolas Ferre <nicolas.fe...@microchip.com>
[claudiu.bez...@microchip.com:
- use SAM9X60's compatible for pinctrl
- add drive strength and slew rate options for SDMMC0 pins.]
Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
[tudor.amba...@microchip.com:
- u-boot,dm-pre-reloc property in dedicated file,
- fix pit len, starts from 0xFFFFFE40 and it is of len 0x10]
Signed-off-by: Tudor Ambarus <tudor.amba...@microchip.com>
---
 arch/arm/dts/Makefile              |   2 +
 arch/arm/dts/sam9x60.dtsi          | 225 +++++++++++++++++++++++++++++++++++++
 arch/arm/dts/sam9x60ek-u-boot.dtsi | 104 +++++++++++++++++
 arch/arm/dts/sam9x60ek.dts         |  19 ++++
 4 files changed, 350 insertions(+)
 create mode 100644 arch/arm/dts/sam9x60.dtsi
 create mode 100644 arch/arm/dts/sam9x60ek-u-boot.dtsi
 create mode 100644 arch/arm/dts/sam9x60ek.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 250b9ba505aa..52027786ef50 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -690,6 +690,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
        at91sam9x25ek.dtb       \
        at91sam9x35ek.dtb
 
+dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb
+
 dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
 
 dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
new file mode 100644
index 000000000000..e880dc0068df
--- /dev/null
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
+ *
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikar...@microchip.com>
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+
+/{
+       model = "Microchip SAM9X60 SoC";
+       compatible = "microchip,sam9x60";
+
+       aliases {
+               serial0 = &dbgu;
+               gpio0 = &pioA;
+               gpio1 = &pioB;
+       };
+
+       clocks {
+               slow_xtal: slow_xtal {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <0>;
+               };
+
+               main_xtal: main_xtal {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <0>;
+               };
+       };
+
+       ahb {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               sdhci0: sdhci-host@80000000 {
+                       compatible = "microchip,sam9x60-sdhci";
+                       reg = <0x80000000 0x300>;
+                       clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
+                       clock-names = "hclock", "multclk", "baseclk";
+                       bus-width = <4>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_sdhci0>;
+               };
+
+               apb {
+                       compatible = "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       dbgu: serial@fffff200 {
+                               compatible = "atmel,at91sam9260-dbgu", 
"atmel,at91sam9260-usart";
+                               reg = <0xfffff200 0x200>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_dbgu>;
+                               clocks = <&dbgu_clk>;
+                               clock-names = "usart";
+                       };
+
+                       pinctrl {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "microchip,sam9x60-pinctrl", 
"simple-bus";
+                               ranges = <0xfffff400 0xfffff400 0x800>;
+                               reg = <0xfffff400 0x200         /* pioA */
+                                      0xfffff600 0x200         /* pioB */
+                                      0xfffff800 0x200         /* pioC */
+                                      0xfffffa00 0x200>;       /* pioD */
+
+                               /* shared pinctrl settings */
+                               dbgu {
+                                       pinctrl_dbgu: dbgu-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 9 
AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+                                                       AT91_PIOA 10 
AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                       };
+                               };
+
+                               sdhci0 {
+                                       pinctrl_sdhci0: sdhci0 {
+                                               atmel,pins =
+                                                       <AT91_PIOA 17 
AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK  periph A with 
pullup */
+                                                        AT91_PIOA 16 
AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA16 CMD periph A with 
pullup */
+                                                        AT91_PIOA 15 
AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA15 DAT0 periph A */
+                                                        AT91_PIOA 18 
AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA18 DAT1 periph A with 
pullup */
+                                                        AT91_PIOA 19 
AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA19 DAT2 periph A with 
pullup */
+                                                        AT91_PIOA 20 
AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;              /* PA20 DAT3 periph A with 
pullup */
+                                       };
+                               };
+                       };
+
+                       pioA: gpio@fffff400 {
+                               compatible = "atmel,at91sam9x5-gpio", 
"atmel,at91rm9200-gpio";
+                               reg = <0xfffff400 0x200>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               clocks = <&pioA_clk>;
+                       };
+
+                       pioB: gpio@fffff600 {
+                               compatible = "atmel,at91sam9x5-gpio", 
"atmel,at91rm9200-gpio";
+                               reg = <0xfffff600 0x200>;
+                               #gpio-cells = <2>;
+                               gpio-controller;
+                               clocks = <&pioB_clk>;
+                       };
+
+                       pmc: pmc@fffffc00 {
+                               compatible = "atmel,at91sam9x5-pmc";
+                               reg = <0xfffffc00 0x200>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               main: mainck {
+                                       compatible = 
"atmel,at91sam9x5-clk-main";
+                                       #clock-cells = <0>;
+                               };
+
+                               plla: pllack {
+                                       compatible = 
"microchip,sam9x60-clk-pll";
+                                       #clock-cells = <0>;
+                                       clocks = <&main>;
+                                       reg = <0>;
+                                       atmel,clk-input-range = <8000000 
24000000>;
+                                       #atmel,pll-clk-output-range-cells = <4>;
+                                       atmel,pll-clk-output-ranges = 
<140000000 1200000000 0 0>;
+                               };
+
+                               mck: masterck {
+                                       compatible = 
"atmel,at91sam9x5-clk-master";
+                                       #clock-cells = <0>;
+                                       clocks = <&md_slck>, <&main>, <&plla>;
+                                       atmel,clk-output-range = <140000000 
200000000>;
+                                       atmel,clk-divisors = <1 2 4 6>;
+                               };
+
+                               periph: periphck {
+                                       compatible = 
"microchip,sam9x60-clk-peripheral";
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       clocks = <&mck>;
+
+                                       pioA_clk: pioA_clk {
+                                               #clock-cells = <0>;
+                                               reg = <2>;
+                                       };
+
+                                       pioB_clk: pioB_clk {
+                                               #clock-cells = <0>;
+                                               reg = <3>;
+                                       };
+
+                                       sdhci0_clk: sdhci0_clk {
+                                               #clock-cells = <0>;
+                                               reg = <12>;
+                                       };
+
+                                       dbgu_clk: dbgu_clk {
+                                               #clock-cells = <0>;
+                                               reg = <47>;
+                                       };
+                               };
+
+                               generic: gck {
+                                       compatible = 
"microchip,sam9x60-clk-generated";
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       clocks = <&md_slck>, <&td_slck>, 
<&main>, <&mck>, <&plla>;
+
+                                       sdhci0_gclk: sdhci0_gclk {
+                                               #clock-cells = <0>;
+                                               reg = <12>;
+                                       };
+                               };
+                       };
+
+                       pit: timer@fffffe40 {
+                               compatible = "atmel,at91sam9260-pit";
+                               reg = <0xfffffe40 0x10>;
+                               clocks = <&mck>;
+                       };
+
+                       slowckc: sckc@fffffe50 {
+                               compatible = "atmel,at91sam9x5-sckc";
+                               reg = <0xfffffe50 0x4>;
+
+                               slow_osc: slow_osc {
+                                       compatible = 
"atmel,at91sam9x5-clk-slow-osc";
+                                       #clock-cells = <0>;
+                                       clocks = <&slow_xtal>;
+                               };
+
+                               slow_rc_osc: slow_rc_osc {
+                                       compatible = 
"atmel,at91sam9x5-clk-slow-rc-osc";
+                                       #clock-cells = <0>;
+                                       clock-frequency = <32768>;
+                               };
+
+                               td_slck: td_slck {
+                                       compatible = 
"atmel,at91sam9x5-clk-slow";
+                                       #clock-cells = <0>;
+                                       clocks = <&slow_rc_osc>, <&slow_osc>;
+                               };
+
+                               md_slck: md_slck {
+                                       compatible = 
"atmel,at91sam9x5-clk-slow";
+                                       #clock-cells = <0>;
+                                       clocks = <&slow_rc_osc>;
+                               };
+                       };
+               };
+       };
+};
diff --git a/arch/arm/dts/sam9x60ek-u-boot.dtsi 
b/arch/arm/dts/sam9x60ek-u-boot.dtsi
new file mode 100644
index 000000000000..68e220926e5e
--- /dev/null
+++ b/arch/arm/dts/sam9x60ek-u-boot.dtsi
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60-u-boot.dts - Device Tree file for SAM9X60 SoC.
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ */
+
+/ {
+       chosen {
+               u-boot,dm-pre-reloc;
+       };
+
+       ahb {
+               u-boot,dm-pre-reloc;
+
+               apb {
+                       u-boot,dm-pre-reloc;
+
+                       pinctrl {
+                               u-boot,dm-pre-reloc;
+                       };
+               };
+       };
+};
+
+&sdhci0 {
+       u-boot,dm-pre-reloc;
+};
+
+&dbgu {
+       u-boot,dm-pre-reloc;
+};
+
+&pinctrl_dbgu {
+       u-boot,dm-pre-reloc;
+};
+
+&pinctrl_sdhci0 {
+       u-boot,dm-pre-reloc;
+};
+
+&pioA {
+       u-boot,dm-pre-reloc;
+};
+
+&pmc {
+       u-boot,dm-pre-reloc;
+};
+
+&main {
+       u-boot,dm-pre-reloc;
+};
+
+&plla {
+       u-boot,dm-pre-reloc;
+};
+
+&mck {
+       u-boot,dm-pre-reloc;
+};
+
+&periph {
+       u-boot,dm-pre-reloc;
+};
+
+&pioA_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&sdhci0_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&dbgu_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&generic {
+       u-boot,dm-pre-reloc;
+};
+
+&sdhci0_gclk {
+       u-boot,dm-pre-reloc;
+};
+
+&slowckc {
+       u-boot,dm-pre-reloc;
+};
+
+&slow_osc {
+       u-boot,dm-pre-reloc;
+};
+
+&slow_rc_osc {
+       u-boot,dm-pre-reloc;
+};
+
+&td_slck {
+       u-boot,dm-pre-reloc;
+};
+
+&md_slck {
+       u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
new file mode 100644
index 000000000000..e64566ec8e58
--- /dev/null
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60ek.dts - Device Tree file for SAM9X60 EK board
+ *
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikar...@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x60.dtsi"
+
+/ {
+       model = "Microchip SAM9X60-Ek";
+       compatible = "microchip,sam9x60ek", "microchip,sam9x60", 
"atmel,at91sam9";
+
+       chosen {
+               stdout-path = &dbgu;
+       };
+};
-- 
2.9.5

_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Reply via email to