On Sun, Jan 22, 2017 at 01:06:47AM +, André Przywara wrote:
> > If we still needs it,
>
> First: we definitely need this symbol, since it guards an implementation
> defined register and the Cortex-A53 does not define it. So we have to
> confine its use to the ARMv7 Cortex CPUs.
Ack.
> > x86
Hi,
On 16/01/17 07:44, Maxime Ripard wrote:
> On Fri, Jan 13, 2017 at 08:28:07AM +, André Przywara wrote:
>> On 13/01/17 08:09, Vishnu Patekar wrote:
>> Hi Vishnu,
>>
>>> Even for the single core cortex-a7, SMP bit should be set before
>>> enabling MMU and cache.
>>>
>>> Reference: Cortex A7 r
On Fri, Jan 13, 2017 at 08:28:07AM +, André Przywara wrote:
> On 13/01/17 08:09, Vishnu Patekar wrote:
> Hi Vishnu,
>
> > Even for the single core cortex-a7, SMP bit should be set before
> > enabling MMU and cache.
> >
> > Reference: Cortex A7 r0p5 TRM. section 4.3.31.
>
> Ah, good point, th
On 13/01/17 08:09, Vishnu Patekar wrote:
Hi Vishnu,
> Even for the single core cortex-a7, SMP bit should be set before
> enabling MMU and cache.
>
> Reference: Cortex A7 r0p5 TRM. section 4.3.31.
Ah, good point, thanks for the heads up. I was misled by the SMP name
when answering Icenowy.
So it'
Even for the single core cortex-a7, SMP bit should be set before
enabling MMU and cache.
Reference: Cortex A7 r0p5 TRM. section 4.3.31.
On Fri, Jan 13, 2017 at 12:41 PM, Icenowy Zheng wrote:
>
>
> 13.01.2017, 09:34, "Andre Przywara" :
>> Instead of enumerating all SoC families that need that bit
5 matches
Mail list logo