09.01.2017, 18:01, "Maxime Ripard" :
> On Fri, Jan 06, 2017 at 06:55:05AM +0800, Icenowy Zheng wrote:
>> > > + MCTL_CR_32BIT /* fixme, thats wrong but what boot0 does */ |
>> >
>> > What's wrong about it?
>>
>> V3s DRAM seems to be 16-bit.
>>
>>
2017年1月9日 下午6:30于 Andre Przywara 写道:
>
> Hi,
>
> On 05/01/17 22:55, Icenowy Zheng wrote:
> >
> > 2017年1月6日 06:37于 Maxime Ripard 写道:
> >>
> >> On Thu, Dec 29, 2016 at 03:00:58AM +0800, Icenowy Zheng wrote:
> >>> H3-like DRAM
Hi,
On 05/01/17 22:55, Icenowy Zheng wrote:
>
> 2017年1月6日 06:37于 Maxime Ripard 写道:
>>
>> On Thu, Dec 29, 2016 at 03:00:58AM +0800, Icenowy Zheng wrote:
>>> H3-like DRAM controller needs some special code to operate a DDR2 DRAM
>>> chip. Add the logic to probe
On Fri, Jan 06, 2017 at 06:55:05AM +0800, Icenowy Zheng wrote:
> > > + MCTL_CR_32BIT /* fixme, thats wrong but what boot0 does */ |
> >
> > What's wrong about it?
>
> V3s DRAM seems to be 16-bit.
>
> However, boot0 has this bit set, and without this bit, it cannot work.
>
> According
2017年1月6日 06:37于 Maxime Ripard 写道:
>
> On Thu, Dec 29, 2016 at 03:00:58AM +0800, Icenowy Zheng wrote:
> > H3-like DRAM controller needs some special code to operate a DDR2 DRAM
> > chip. Add the logic to probe such a chip.
> >
> > As there's no commercial
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