Fifo width could be different on different socs, e.g. stv0991 & altera soc
have different fifo width.
Signed-off-by: Vikas Manocha <vikas.mano...@st.com>
---
Changes in v2: Rebased to master
arch/arm/dts/socfpga.dtsi | 1 +
arch/arm/dts/stv0991.dts | 1 +
drivers/spi/cadence_qspi.c | 1 +
drivers/spi/cadence_qspi.h | 1 +
drivers/spi/cadence_qspi_apb.c | 13 ++++---------
5 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 1099a92..ee43762 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -640,6 +640,7 @@
ext-decoder = <0>; /* external decoder */
num-cs = <4>;
fifo-depth = <128>;
+ fifo-width = <4>;
sram-size = <128>;
bus-num = <2>;
status = "disabled";
diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
index e23d4fd..f0f450b 100644
--- a/arch/arm/dts/stv0991.dts
+++ b/arch/arm/dts/stv0991.dts
@@ -34,6 +34,7 @@
<0x40000000 0x0000010>;
clocks = <3750000>;
sram-size = <256>;
+ fifo-width = <8>;
status = "okay";
flash0: n25q32@0 {
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 95c9cea..bfcd39e 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -311,6 +311,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice
*bus)
plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
+ plat->fifo_width = fdtdec_get_int(blob, node, "fifo-width", 4);
debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \
page-size=%d\n", __func__, plat->regbase, plat->flashbase,
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 7341339..91f38f1 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -27,6 +27,7 @@ struct cadence_spi_platdata {
u32 tchsh_ns;
u32 tslch_ns;
u32 sram_size;
+ u32 fifo_width;
};
struct cadence_spi_priv {
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e11f715..e5da225 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -34,8 +34,6 @@
#define CQSPI_REG_RETRY (10000)
#define CQSPI_POLL_IDLE_RETRY (3)
-#define CQSPI_FIFO_WIDTH (4)
-
#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
/* Transfer mode */
@@ -48,9 +46,6 @@
#define CQSPI_DUMMY_CLKS_PER_BYTE (8)
#define CQSPI_DUMMY_BYTES_MAX (4)
-
-#define CQSPI_REG_SRAM_FILL_THRESHOLD \
- ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
/****************************************************************************
* Controller's configuration and status register (offset from QSPI_BASE)
****************************************************************************/
@@ -230,11 +225,11 @@ static int qpsi_write_sram_fifo_push(struct
cadence_spi_platdata *plat,
page_size : remaining;
remaining -= wr_bytes;
- while (wr_bytes >= CQSPI_FIFO_WIDTH) {
- for (i = 0; i < CQSPI_FIFO_WIDTH/sizeof(dest_addr); i++)
+ while (wr_bytes >= plat->fifo_width) {
+ for (i = 0; i < plat->fifo_width/sizeof(dest_addr); i++)
writel(*(src_ptr+i), dest_addr+i);
- src_ptr += CQSPI_FIFO_WIDTH/sizeof(dest_addr);
- wr_bytes -= CQSPI_FIFO_WIDTH;
+ src_ptr += plat->fifo_width/sizeof(dest_addr);
+ wr_bytes -= plat->fifo_width;
}
if (wr_bytes) {
/* dangling bytes */
--
1.7.9.5
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